TY - GEN
T1 - Real chip performance evaluation on through chip interface IP for renesas SOTB 65nm process
AU - Kayashima, Hideto
AU - Kojima, Takuya
AU - Okuhara, Hayate
AU - Shidei, Tsunaaki
AU - Amano, Hideharu
N1 - Funding Information:
ACKNOWLEDGEMENT This study was supported by JSPS KAKENHI (S) building block computing system and JSPS KAKENHI (B) building block computing system with a chip-bridge stacking scheme. The chip design was performed by the University of Tokyo Large Scale Integrated System Design Education and Research Center (VDEC) using Synopsys, Cadence, and Mentor CAD. The PDK used in the research was made in cooperation with Renesas Electronics Corporation and Nippon Systemware Corporation through VDEC. We are deeply grateful to everyone involved.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/11
Y1 - 2019/11
N2 - The building block computing system can build various systems by connecting small-sized chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). First, we have developed TCI IP by using the Renesas 65nm SOTB process and verified it with a simple TEG chip. Then several family chips have been developed with the IP; Geyser-TT (MIPS R3000 compatible processor), SNACC (neural network accelerator), CC-SOTB2 (improved CGRA), KVS (the accelerator for Key-Value-Store database), and SMTT (Shared Memory for Twin Tower). All of these chips worked alone without problems. However, when these chips were stacked to construct a system, problems were found on some combination of chips that TCI did not operate as designed. To investigate the cause of the trouble, we have developed a sophisticated tester chip called the TCI Tester. It provides three modes: RAW mode in which handshake lines can be directly controlled, CUBE mode in which the TCI Tester can write the data into the stacked target chips, and LOOP mode which allows continuous write and read operation for a long time working test. Through the evaluation by using a two-TCI Tester stacking system, the following appeared. (1) The maximum transfer frequency of the TCI IP is much lower than 50MHz which is the target value. Only 14MHz for the downward and 9MHz for the upward. (2) The performance of the upward transfer is lower than that of the downward. The poor upward data transfer performance comes from that the voltage drop on the power grid becomes large because of the location of the upward transmitter coil. We can improve it by increasing the number of power pads for the transmitter and enhancing the power grid. However, with the low transfer frequency, the TCI IP worked more than a day continuously.
AB - The building block computing system can build various systems by connecting small-sized chips with inductive coupling wireless chip-to-chip connection TCI (Through Chip Interface). First, we have developed TCI IP by using the Renesas 65nm SOTB process and verified it with a simple TEG chip. Then several family chips have been developed with the IP; Geyser-TT (MIPS R3000 compatible processor), SNACC (neural network accelerator), CC-SOTB2 (improved CGRA), KVS (the accelerator for Key-Value-Store database), and SMTT (Shared Memory for Twin Tower). All of these chips worked alone without problems. However, when these chips were stacked to construct a system, problems were found on some combination of chips that TCI did not operate as designed. To investigate the cause of the trouble, we have developed a sophisticated tester chip called the TCI Tester. It provides three modes: RAW mode in which handshake lines can be directly controlled, CUBE mode in which the TCI Tester can write the data into the stacked target chips, and LOOP mode which allows continuous write and read operation for a long time working test. Through the evaluation by using a two-TCI Tester stacking system, the following appeared. (1) The maximum transfer frequency of the TCI IP is much lower than 50MHz which is the target value. Only 14MHz for the downward and 9MHz for the upward. (2) The performance of the upward transfer is lower than that of the downward. The poor upward data transfer performance comes from that the voltage drop on the power grid becomes large because of the location of the upward transmitter coil. We can improve it by increasing the number of power pads for the transmitter and enhancing the power grid. However, with the low transfer frequency, the TCI IP worked more than a day continuously.
KW - Building Block Computing System
KW - SOTB (Silicon On Thin Buried Oxide)
KW - Through Chip Interface
UR - http://www.scopus.com/inward/record.url?scp=85078824511&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85078824511&partnerID=8YFLogxK
U2 - 10.1109/CANDARW.2019.00054
DO - 10.1109/CANDARW.2019.00054
M3 - Conference contribution
AN - SCOPUS:85078824511
T3 - Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019
SP - 269
EP - 274
BT - Proceedings - 2019 7th International Symposium on Computing and Networking Workshops, CANDARW 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th International Symposium on Computing and Networking Workshops, CANDARW 2019
Y2 - 26 November 2019 through 29 November 2019
ER -