Reconfigurable phase-locked loops on FPGA utilizing intrinsic synchronizability

H. Tanaka; A. Hasegawa; S. Haruyama

doi:10.1049/el:20010051

Reconfigurable phase-locked loops on FPGA utilizing intrinsic synchronizability

H. Tanaka, A. Hasegawa, S. Haruyama

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

A new digital phase-locked loop (PLL) tested on a field programmable gate array (FPGA) was designed. Intrinsic synchronizability of electrical operators was utilized by PLL. Dynamically reconfigurable clock networks was provided by PLL which did not require an analog element like control voltage.

Original language	English
Pages (from-to)	77-78
Number of pages	2
Journal	Electronics Letters
Volume	37
Issue number	2
DOIs	https://doi.org/10.1049/el:20010051
Publication status	Published - 2001 Jan 18
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:20010051

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title = "Reconfigurable phase-locked loops on FPGA utilizing intrinsic synchronizability",

abstract = "A new digital phase-locked loop (PLL) tested on a field programmable gate array (FPGA) was designed. Intrinsic synchronizability of electrical operators was utilized by PLL. Dynamically reconfigurable clock networks was provided by PLL which did not require an analog element like control voltage.",

author = "H. Tanaka and A. Hasegawa and S. Haruyama",

year = "2001",

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doi = "10.1049/el:20010051",

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AU - Hasegawa, A.

AU - Haruyama, S.

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N2 - A new digital phase-locked loop (PLL) tested on a field programmable gate array (FPGA) was designed. Intrinsic synchronizability of electrical operators was utilized by PLL. Dynamically reconfigurable clock networks was provided by PLL which did not require an analog element like control voltage.

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Reconfigurable phase-locked loops on FPGA utilizing intrinsic synchronizability

Abstract

ASJC Scopus subject areas

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