Reconfigurable systolic Viterbi decoder

Kazuya Takahashi, Hiroshi Tobita, Shinnichiro Haruyama, Masao Nakagawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)


This paper introduces a new algorithm which saves the power consumption of the systolic Viterbi decoder. The new algorithm dynamically changes the trucated path length of a Viterbi decoder according to the channel condition, resulting in reduction of power consumption. This algorithm is based on the observation that the truncated path length and bit error rate are closely related. If we set the truncated path length short, we can reduce the size of the decoder even though the system performance is sacrificed. We propose reconfiguration of the truncated path length according to channel state. It is shown that power consumption of a systolic Viterbi decoder with convolutional code for a constraint length K = 3 and a code rate R = 1/2 can be eliminated over 20 percent at the bit error rate of 10-3 in a Rayleigh fading channel. Furthermore, the longer the truncated path length becomes, the more effective the proposed method is.

Original languageEnglish
Title of host publicationIEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall
Number of pages4
Publication statusPublished - 1999 Dec 1
EventIEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall - Amsterdam, Netherlands
Duration: 1999 Sept 191999 Sept 22

Publication series

NameIEEE Vehicular Technology Conference
ISSN (Print)1550-2252


OtherIEEE VTS 50th Vehicular Technology Conference, VTC 1999-Fall

ASJC Scopus subject areas

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Applied Mathematics


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