Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

Kazuei Hironaka; Masayuki Kimura; Yoshiki Saito; Toru Sano; Masaru Kato; Vasutan Tunbunheng; Yoshihiro Yasuda; Hideharu Amano

doi:10.1109/FPT.2010.5681431

Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

The Partially Fixed Configuration Mapping (PFCM) is a context mapping technique for Dynamically Reconfigurable Processor Array (DRPA) focusing on reducing the power consumption. It assigns operations into Processing Elements (PEs) so as to keep the configuration of the previous context as possible. It reduces the changing part of the datapath structure on the PE array as well as its switching frequency. Preliminary evaluation results show that it can reduce the computing power by 6.7% - 11.3%. The demonstration shows the power reduction directly by using the real chip MuCCRA-3, a prototype of DRPA executing signal processing applications with and without applying PFCM. The design environment for using PFCM is also exhibited.

Original language	English
Title of host publication	Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
Pages	349-352
Number of pages	4
DOIs	https://doi.org/10.1109/FPT.2010.5681431
Publication status	Published - 2010 Dec 1
Event	2010 International Conference on Field-Programmable Technology, FPT'10 - Beijing, China Duration: 2010 Dec 8 → 2010 Dec 10

Publication series

Name	Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10

Other

Other	2010 International Conference on Field-Programmable Technology, FPT'10
Country/Territory	China
City	Beijing
Period	10/12/8 → 10/12/10

ASJC Scopus subject areas

Computational Theory and Mathematics
Computer Science Applications

Access to Document

10.1109/FPT.2010.5681431

Cite this

Hironaka, K., Kimura, M., Saito, Y., Sano, T., Kato, M., Tunbunheng, V., Yasuda, Y., & Amano, H. (2010). Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping. In Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10 (pp. 349-352). Article 5681431 (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10). https://doi.org/10.1109/FPT.2010.5681431

Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping. / Hironaka, Kazuei; Kimura, Masayuki; Saito, Yoshiki et al.
Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. 2010. p. 349-352 5681431 (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Hironaka, K, Kimura, M, Saito, Y, Sano, T, Kato, M, Tunbunheng, V, Yasuda, Y & Amano, H 2010, Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping. in Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10., 5681431, Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10, pp. 349-352, 2010 International Conference on Field-Programmable Technology, FPT'10, Beijing, China, 10/12/8. https://doi.org/10.1109/FPT.2010.5681431

Hironaka K, Kimura M, Saito Y, Sano T, Kato M, Tunbunheng V et al. Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping. In Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. 2010. p. 349-352. 5681431. (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10). doi: 10.1109/FPT.2010.5681431

Hironaka, Kazuei ; Kimura, Masayuki ; Saito, Yoshiki et al. / Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping. Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10. 2010. pp. 349-352 (Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10).

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AU - Tunbunheng, Vasutan

AU - Yasuda, Yoshihiro

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Reducing power consumption for dynamically reconfigurable processor array with partially fixed configuration mapping

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