Reduction calculator in an FPGA based switching Hub for high performance clusters

Takuya Kuhara; Chiharu Tsuruta; Toshihiro Hanawa; Hideharu Amano

doi:10.1109/FPL.2015.7293985

Reduction calculator in an FPGA based switching Hub for high performance clusters

Takuya Kuhara, Chiharu Tsuruta, Toshihiro Hanawa, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

10 Citations (Scopus)

Abstract

Unused logic in the field-programmable gate array (FPGA) for the switching hub is one potential resource to accelerate the computation of data exchanged through the hub. However, for large scale scientific computation, it is difficult to implement such an accelerator on the FPGA used in high performance computers. Here, a reduction calculator for executing ARGOT (accelerated radiative transfer on grids using oct-tree) to solve the radiative transfer equation used for simulation of astronomical objects is implemented on the FPGA of PEACH2 (PCI Express Adaptive Communication Hub ver2), a low latency switching hub for high performance GPU (graphics processor unit) clusters. The implemented reduction calculator uses a pipelined tree of adders and works with a 150-MHz clock without affecting the switching hub functions. Use of the DMA (direct memory access) transfer with descriptors made it possible to improve the performance of CPU excution by a maximum of about 45 times in a real system.

Original language	English
Title of host publication	25th International Conference on Field Programmable Logic and Applications, FPL 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	9780993428005
DOIs	https://doi.org/10.1109/FPL.2015.7293985
Publication status	Published - 2015 Oct 7
Event	25th International Conference on Field Programmable Logic and Applications, FPL 2015 - London, United Kingdom Duration: 2015 Sept 2 → 2015 Sept 4

Other

Other	25th International Conference on Field Programmable Logic and Applications, FPL 2015
Country/Territory	United Kingdom
City	London
Period	15/9/2 → 15/9/4

ASJC Scopus subject areas

Hardware and Architecture
Signal Processing
Software
Computer Science Applications

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10.1109/FPL.2015.7293985

Cite this

Reduction calculator in an FPGA based switching Hub for high performance clusters. / Kuhara, Takuya; Tsuruta, Chiharu; Hanawa, Toshihiro et al.
25th International Conference on Field Programmable Logic and Applications, FPL 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7293985.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kuhara, T, Tsuruta, C, Hanawa, T & Amano, H 2015, Reduction calculator in an FPGA based switching Hub for high performance clusters. in 25th International Conference on Field Programmable Logic and Applications, FPL 2015., 7293985, Institute of Electrical and Electronics Engineers Inc., 25th International Conference on Field Programmable Logic and Applications, FPL 2015, London, United Kingdom, 15/9/2. https://doi.org/10.1109/FPL.2015.7293985

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Reduction calculator in an FPGA based switching Hub for high performance clusters

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