Research challenges on 2-D and 3-D network-on-chips

Hiroki Matsutani

doi:10.1109/CANDAR.2013.12

Research challenges on 2-D and 3-D network-on-chips

Hiroki Matsutani

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

The advances in semiconductor technology allow us to integrate a number of processing cores on a single chip or a single package. These many-core processors are expected to boost a wide range of applications from high-performance computing, cyber-physical computing, cloud, and big data processing. This tutorial first introduces recent many-core processors and then focuses on fundamental technologies of 2-D and 3-D Network-on-Chip architectures in terms of network topology, routing algorithm, and router architecture. Recent research challenges on 2-D and 3-D Network-on-Chip architectures, such as 2-D and 3-D wireless technologies, are also surveyed.

Original language	English
Title of host publication	Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013
Pages	24-25
Number of pages	2
DOIs	https://doi.org/10.1109/CANDAR.2013.12
Publication status	Published - 2013 Dec 1
Event	2013 1st International Symposium on Computing and Networking, CANDAR 2013 - Matsuyama, Ehime, Japan Duration: 2013 Dec 4 → 2013 Dec 6

Publication series

Name	Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013

Other

Other	2013 1st International Symposium on Computing and Networking, CANDAR 2013
Country/Territory	Japan
City	Matsuyama, Ehime
Period	13/12/4 → 13/12/6

Keywords

3-D NoCs
Network-on-Chips (NoCs)
interconnection networks

ASJC Scopus subject areas

Computer Networks and Communications

Access to Document

10.1109/CANDAR.2013.12

Cite this

Matsutani, H 2013, Research challenges on 2-D and 3-D network-on-chips. in Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013., 6726874, Proceedings - 2013 1st International Symposium on Computing and Networking, CANDAR 2013, pp. 24-25, 2013 1st International Symposium on Computing and Networking, CANDAR 2013, Matsuyama, Ehime, Japan, 13/12/4. https://doi.org/10.1109/CANDAR.2013.12

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KW - interconnection networks

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Research challenges on 2-D and 3-D network-on-chips

Abstract

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Keywords

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