TY - JOUR
T1 - Rotary coding for power reduction and S/N improvement in inductive-coupling data communication
AU - Radecki, Andrzej
AU - Miura, Noriyuki
AU - Ishikuro, Hiroki
AU - Kuroda, Tadahiro
N1 - Funding Information:
Manuscript received February 03, 2012; revised May 04, 2012; accepted June 21, 2012. Date of publication September 12, 2012; date of current version October 26, 2012. This paper was approved by Guest Editors Shen-Iuan Liu and Tsung-Hsien Lin. This work was supported by a grant from CREST/JST.
PY - 2012
Y1 - 2012
N2 - In this paper, we describe a noncontact inductive-coupling data transmission link employing rotary data encoding. A system using this data-transmission link is inherently insensitive to jitter introduced in the channel and consumes approximately 50% less power than previously reported solutions. The system is targeted for applications benefiting from simultaneous noncontact power and data transmission, such as wafer-level testing, memory card interfaces, and inter-strata data communication in 3-D integrated circuits. Functionality of the proposed link is verified experimentally with a test chip developed in an 0.18-μm CMOS process. In the second part of this paper, we introduce a design of a high-speed data transceiver using rotary coding. We demonstrate that, because of properties of the rotary coding, a simple transceiver without a PLL-based CDR circuit can operate at data rates limited only by characteristics of the physical channel. For performance optimization, we have developed a new family of ternary logic gates including latches, D-flip-flops, and multiplexers.
AB - In this paper, we describe a noncontact inductive-coupling data transmission link employing rotary data encoding. A system using this data-transmission link is inherently insensitive to jitter introduced in the channel and consumes approximately 50% less power than previously reported solutions. The system is targeted for applications benefiting from simultaneous noncontact power and data transmission, such as wafer-level testing, memory card interfaces, and inter-strata data communication in 3-D integrated circuits. Functionality of the proposed link is verified experimentally with a test chip developed in an 0.18-μm CMOS process. In the second part of this paper, we introduce a design of a high-speed data transceiver using rotary coding. We demonstrate that, because of properties of the rotary coding, a simple transceiver without a PLL-based CDR circuit can operate at data rates limited only by characteristics of the physical channel. For performance optimization, we have developed a new family of ternary logic gates including latches, D-flip-flops, and multiplexers.
KW - Binary codes
KW - channel coding
KW - data communication
KW - decoding
KW - encoding
KW - flip-flops
KW - inductive power transmission
KW - logic gates
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U2 - 10.1109/JSSC.2012.2211656
DO - 10.1109/JSSC.2012.2211656
M3 - Article
AN - SCOPUS:84869238629
SN - 0018-9200
VL - 47
SP - 2643
EP - 2653
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 11
M1 - 6301782
ER -