TY - GEN
T1 - SCIMA-SMP
T2 - 3rd Workshop on Memory Performance Issues, WMPI '04, in Conjunction with the 31st International Symposium on Computer Architecture
AU - Takahashi, Chikafumi
AU - Kondo, Masaaki
AU - Boku, Taisuke
AU - Takahashi, Daisuke
AU - Nakamura, Hiroshi
AU - Sato, Mitsuhisa
PY - 2004
Y1 - 2004
N2 - In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software Controlled Integrated Memory Architecture for SMP) with the intent of solving the performance gap problem between a processor and off-chip memory. With special instructions which enable the explicit data transfer between on-chip memory and off-chip memory, this architecture is able to control the data transfer timing and its granularity by the application program, and the SMP bus is utilized efficiently compared with traditional cache-only architecture. Through the performance evaluation based on clock-level simulation for various HPC applications, we confirmed that this architecture largely reduces the bus access cycle by avoiding redundant data transfer and controlling the granularity of the data movement between on-chip and off-chip memory.
AB - In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software Controlled Integrated Memory Architecture for SMP) with the intent of solving the performance gap problem between a processor and off-chip memory. With special instructions which enable the explicit data transfer between on-chip memory and off-chip memory, this architecture is able to control the data transfer timing and its granularity by the application program, and the SMP bus is utilized efficiently compared with traditional cache-only architecture. Through the performance evaluation based on clock-level simulation for various HPC applications, we confirmed that this architecture largely reduces the bus access cycle by avoiding redundant data transfer and controlling the granularity of the data movement between on-chip and off-chip memory.
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U2 - 10.1145/1054943.1054960
DO - 10.1145/1054943.1054960
M3 - Conference contribution
AN - SCOPUS:77954445736
SN - 159593040X
SN - 9781595930408
T3 - ACM International Conference Proceeding Series
SP - 121
EP - 128
BT - Proceedings of the 3rd Workshop on Memory Performance Issues, WMPI '04, in Conjunction with the 31st International Symposium on Computer Architecture
Y2 - 20 June 2004 through 20 June 2004
ER -