The self-heating effects (SHEs) of bulk and silicon-on-insulator (SOI) fin-type field-effect transistors (FinFETs) and their impacts on circuit performance have been investigated on the basis of a realistic thermal conductivity of silicon. The heat dissipation via interconnect wires and interface thermal resistance in the high- gate stack were incorporated in simulations. It is shown that the depth of the shallow trench isolation (STI) of bulk FinFETs cannot be decreased to less than 100nm owing to the increase in off-state leakage current. We observed that the thermal resistance Rth of SOI FinFETs greatly decreases upon thinning the buried oxide (BOX) layer. When the BOX thickness tBOX is less than 50 nm, the Rth of SOI FinFETs is smaller than that of bulk FinFETs with an STI thickness of 100 nm, indicating a lower operation temperature of the thin-BOX SOI FinFETs than that of bulk FinFETs. The lower operation temperature of the 5-nm BOX SOI FinFET was confirmed under a practical bias condition for analog operations. In fin width, Wfin , versus Rth characteristics, a strong Wfin dependence of Rth was observed only in the bulk FinFETs, implying that fluctuations in Wfin result in the variability of the operation temperature of the bulk FinFETs. Analog performance has been analyzed by calculating the cutoff frequency fT and the maximum oscillation frequency fmax. We demonstrated that both fT and fmax can be maximized in SOI FinFETs by optimizing tBOX with regard to electrical and thermal properties. Better analog performance, and hence the optimization of tBOX, are indispensable for the device design of a FinFET-based system-on-a-chip (SoC) platform.
ASJC Scopus subject areas
- General Engineering
- General Physics and Astronomy