Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions

M. Saitoh; Y. Nakabayashi; H. Itokawa; M. Murano; I. Mizushima; K. Uchida; T. Numata

doi:10.1109/VLSIT.2010.5556214

Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions

M. Saitoh, Y. Nakabayashi, H. Itokawa, M. Murano, I. Mizushima, K. Uchida, T. Numata

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

39 Citations (Scopus)

Abstract

We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<10nm). I_d variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <100> NW instead of <110> NW, I_on = 1mA/μm for I_off = 100nA/μm is achieved without stress techniques. Long-L mobility (μ) was systematically studied by separating top and side channel μ. μ of <100> nFETs and <110> pFETs (potentially-high ?) largely degrade due to side-surface roughness. Gate stress and interface traps affect μ?of <110> nFETs and <110> pFETs, respectively.

Original language	English
Title of host publication	2010 Symposium on VLSI Technology, VLSIT 2010
Pages	169-170
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2010.5556214
Publication status	Published - 2010
Externally published	Yes
Event	2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States Duration: 2010 Jun 15 → 2010 Jun 17

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2010 Symposium on VLSI Technology, VLSIT 2010
Country/Territory	United States
City	Honolulu, HI
Period	10/6/15 → 10/6/17

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/VLSIT.2010.5556214

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Saitoh, M., Nakabayashi, Y., Itokawa, H., Murano, M., Mizushima, I., Uchida, K., & Numata, T. (2010). Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. In 2010 Symposium on VLSI Technology, VLSIT 2010 (pp. 169-170). Article 5556214 (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2010.5556214

Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. / Saitoh, M.; Nakabayashi, Y.; Itokawa, H. et al.
2010 Symposium on VLSI Technology, VLSIT 2010. 2010. p. 169-170 5556214 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Saitoh, M, Nakabayashi, Y, Itokawa, H, Murano, M, Mizushima, I, Uchida, K & Numata, T 2010, Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. in 2010 Symposium on VLSI Technology, VLSIT 2010., 5556214, Digest of Technical Papers - Symposium on VLSI Technology, pp. 169-170, 2010 Symposium on VLSI Technology, VLSIT 2010, Honolulu, HI, United States, 10/6/15. https://doi.org/10.1109/VLSIT.2010.5556214

Saitoh M, Nakabayashi Y, Itokawa H, Murano M, Mizushima I, Uchida K et al. Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions. In 2010 Symposium on VLSI Technology, VLSIT 2010. 2010. p. 169-170. 5556214. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2010.5556214

@inproceedings{274b0f8f03d74a529ddcad624e1de8bd,

title = "Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions",

abstract = "We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<10nm). Id variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <100> NW instead of <110> NW, Ion = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Long-L mobility (μ) was systematically studied by separating top and side channel μ. μ of <100> nFETs and <110> pFETs (potentially-high ?) largely degrade due to side-surface roughness. Gate stress and interface traps affect μ?of <110> nFETs and <110> pFETs, respectively.",

author = "M. Saitoh and Y. Nakabayashi and H. Itokawa and M. Murano and I. Mizushima and K. Uchida and T. Numata",

note = "Funding Information: A part of this work was financially supportedb y the Kurata Foundation and the; 2010 Symposium on VLSI Technology, VLSIT 2010 ; Conference date: 15-06-2010 Through 17-06-2010",

year = "2010",

doi = "10.1109/VLSIT.2010.5556214",

language = "English",

isbn = "9781424476374",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "169--170",

booktitle = "2010 Symposium on VLSI Technology, VLSIT 2010",

}

TY - GEN

T1 - Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions

AU - Saitoh, M.

AU - Nakabayashi, Y.

AU - Itokawa, H.

AU - Murano, M.

AU - Mizushima, I.

AU - Uchida, K.

AU - Numata, T.

N1 - Funding Information: A part of this work was financially supportedb y the Kurata Foundation and the

PY - 2010

Y1 - 2010

N2 - We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<10nm). Id variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <100> NW instead of <110> NW, Ion = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Long-L mobility (μ) was systematically studied by separating top and side channel μ. μ of <100> nFETs and <110> pFETs (potentially-high ?) largely degrade due to side-surface roughness. Gate stress and interface traps affect μ?of <110> nFETs and <110> pFETs, respectively.

AB - We successfully reduced the parasitic resistance of nanowire transistors (NW Tr.) by raised S/D extensions with thin spacers (<10nm). Id variations are suppressed by spacer thinning and parasitic capacitance increase is minimal. By adopting <100> NW instead of <110> NW, Ion = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Long-L mobility (μ) was systematically studied by separating top and side channel μ. μ of <100> nFETs and <110> pFETs (potentially-high ?) largely degrade due to side-surface roughness. Gate stress and interface traps affect μ?of <110> nFETs and <110> pFETs, respectively.

UR - http://www.scopus.com/inward/record.url?scp=77957886518&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77957886518&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2010.5556214

DO - 10.1109/VLSIT.2010.5556214

M3 - Conference contribution

AN - SCOPUS:77957886518

SN - 9781424476374

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 169

EP - 170

BT - 2010 Symposium on VLSI Technology, VLSIT 2010

T2 - 2010 Symposium on VLSI Technology, VLSIT 2010

Y2 - 15 June 2010 through 17 June 2010

ER -

Short-channel performance and mobility analysis of <110>- and <100>-Oriented tri-gate nanowire MOSFETs with raised source/drain extensions

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