TY - GEN
T1 - Silicon Isotope Technology for Quantum Computing
AU - Miyamoto, Satoru
AU - Itoh, Kohei M.
N1 - Funding Information:
ACKNOWLEDGMENT We gratefully acknowledge Y. Hoshi, M. Kuroda, and N. Usami for fruitful collaborations, and S. Neyens, T. McJunkin, and M. A. Eriksson for the low-temperature transport measurements. This work has been supported by the KAKENHI (S) No. 26220602 and Spintronics Research Network of Japan.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - We present isotopically engineered Si-28/SiGe heterostructures for development of silicon-based quantum computers using a standard silicon CMOS integration technology. Our Si-28 quantum-wells are well-strained and demonstrate high electron mobility and large valley-splitting. These properties provide promising platforms for realization of highly integrated spin qubits working together with silicon CMOS circuits.
AB - We present isotopically engineered Si-28/SiGe heterostructures for development of silicon-based quantum computers using a standard silicon CMOS integration technology. Our Si-28 quantum-wells are well-strained and demonstrate high electron mobility and large valley-splitting. These properties provide promising platforms for realization of highly integrated spin qubits working together with silicon CMOS circuits.
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U2 - 10.1109/IEDM.2018.8614609
DO - 10.1109/IEDM.2018.8614609
M3 - Conference contribution
AN - SCOPUS:85061826605
T3 - Technical Digest - International Electron Devices Meeting, IEDM
SP - 6.4.1-6.4.4
BT - 2018 IEEE International Electron Devices Meeting, IEDM 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 64th Annual IEEE International Electron Devices Meeting, IEDM 2018
Y2 - 1 December 2018 through 5 December 2018
ER -