TY - GEN
T1 - SNAIL
T2 - 23rd International Conference on Parallel Processing, ICPP 1994
AU - Sasahara, Masashi
AU - Terada, Jun
AU - Zhou, Luo
AU - Gaye, Kalidou
AU - Yamato, Jun Ichi
AU - Ogura, Satoshi
AU - Amano, Hideharu
PY - 1994/1/1
Y1 - 1994/1/1
N2 - Simple Serial Synchronized (SSS) Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called SNAIL with the SSS-MIN are presented. The heart of SNAIL is the prototype 1 μ CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs with 50MHz clock. The message combining is implemented only with 20% increases of the hardware. From the empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSSMIN are tolerable, and the bandwidth of the SSS-MIN is sufficient. Although the performance improvement with the bit serial message combine is not so large (1%) when instructions are stored in the local memory, it becomes up to 400% when instructions are stored in the shared memory.
AB - Simple Serial Synchronized (SSS) Multistage Interconnection Network (MIN) is a novel MIN architecture for connecting processors and memory modules in multiprocessors. Synchronized bit-serial communication simplifies the structure/control, and also solves the pin-limitation problem. Here, design, implementation, and evaluation of a multiprocessor prototype called SNAIL with the SSS-MIN are presented. The heart of SNAIL is the prototype 1 μ CMOS SSS-MIN gate array chip which exchanges packets from 16 inputs with 50MHz clock. The message combining is implemented only with 20% increases of the hardware. From the empirical evaluation with some application programs, it appears that the latency and synchronization overhead of the SSSMIN are tolerable, and the bandwidth of the SSS-MIN is sufficient. Although the performance improvement with the bit serial message combine is not so large (1%) when instructions are stored in the local memory, it becomes up to 400% when instructions are stored in the shared memory.
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U2 - 10.1109/ICPP.1994.182
DO - 10.1109/ICPP.1994.182
M3 - Conference contribution
AN - SCOPUS:18844373761
SN - 0849324939
SN - 9780849324932
T3 - Proceedings of the International Conference on Parallel Processing
SP - I117-I120
BT - Proceedings of the 1994 International Conference on Parallel Processing, ICPP 1994
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 15 August 1994 through 19 August 1994
ER -