SOI tri-gate nanowire MOSFETs for ultra-low power LSI

Masumi Saitoh, Kensuke Ota, Chika Tanaka, Ken Uchida, Toshinori Numata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Nanowire transistors (NW Tr.) are very promising for ultralow-power LSI [1-3]. However, Ion of reported 10nm-size NW Tr., essential for 10nm-Lg scaling, is relatively low due to large parasitic resistance (RSD) and immature performance boosters. Also, dynamic power control using substrate bias (Vsub) and circuit performance under low-V dd operation have not been sufficiently explored yet in NW Tr.

Original languageEnglish
Title of host publication2012 IEEE International SOI Conference, SOI 2012
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 IEEE International SOI Conference, SOI 2012 - Napa, CA, United States
Duration: 2012 Oct 12012 Oct 4

Publication series

NameProceedings - IEEE International SOI Conference
ISSN (Print)1078-621X

Other

Other2012 IEEE International SOI Conference, SOI 2012
Country/TerritoryUnited States
CityNapa, CA
Period12/10/112/10/4

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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