TY - GEN
T1 - Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel
AU - Numata, Toshinori
AU - Saitoh, Masumi
AU - Nakabayashi, Yukio
AU - Ota, Kensuke
AU - Uchida, Ken
PY - 2010
Y1 - 2010
N2 - We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting 〈100〉 NW channel instead of 〈110〉 NW, I on = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW. Ion increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.
AB - We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting 〈100〉 NW channel instead of 〈110〉 NW, I on = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW. Ion increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.
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U2 - 10.1109/ICSICT.2010.5667859
DO - 10.1109/ICSICT.2010.5667859
M3 - Conference contribution
AN - SCOPUS:78751502445
SN - 9781424457984
T3 - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
SP - 37
EP - 40
BT - ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
T2 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
Y2 - 1 November 2010 through 4 November 2010
ER -