Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

Toshinori Numata; Masumi Saitoh; Yukio Nakabayashi; Kensuke Ota; Ken Uchida

doi:10.1109/ICSICT.2010.5667859

Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

Toshinori Numata, Masumi Saitoh, Yukio Nakabayashi, Kensuke Ota, Ken Uchida

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<10nm) and by stress induced from heavily-doped gate. I_d variations are suppressed by the spacer thinning. By adopting 〈100〉 NW channel instead of 〈110〉 NW, I _on = 1mA/μm for I_off = 100nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW. I_on increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.

Original language	English
Title of host publication	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages	37-40
Number of pages	4
DOIs	https://doi.org/10.1109/ICSICT.2010.5667859
Publication status	Published - 2010
Externally published	Yes
Event	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: 2010 Nov 1 → 2010 Nov 4

Publication series

Name	ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other	2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology
Country/Territory	China
City	Shanghai
Period	10/11/1 → 10/11/4

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ICSICT.2010.5667859

Cite this

Numata, T., Saitoh, M., Nakabayashi, Y., Ota, K., & Uchida, K. (2010). Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 37-40). Article 5667859 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2010.5667859

Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel. / Numata, Toshinori; Saitoh, Masumi; Nakabayashi, Yukio et al.
ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 37-40 5667859 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Numata, T, Saitoh, M, Nakabayashi, Y, Ota, K & Uchida, K 2010, Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel. in ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 5667859, ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings, pp. 37-40, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 10/11/1. https://doi.org/10.1109/ICSICT.2010.5667859

Numata T, Saitoh M, Nakabayashi Y, Ota K, Uchida K. Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel. In ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. p. 37-40. 5667859. (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings). doi: 10.1109/ICSICT.2010.5667859

Numata, Toshinori ; Saitoh, Masumi ; Nakabayashi, Yukio et al. / Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel. ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2010. pp. 37-40 (ICSICT-2010 - 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

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abstract = "We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting 〈100〉 NW channel instead of 〈110〉 NW, I on = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW. Ion increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.",

author = "Toshinori Numata and Masumi Saitoh and Yukio Nakabayashi and Kensuke Ota and Ken Uchida",

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AU - Numata, Toshinori

AU - Saitoh, Masumi

AU - Nakabayashi, Yukio

AU - Ota, Kensuke

AU - Uchida, Ken

PY - 2010

Y1 - 2010

N2 - We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting 〈100〉 NW channel instead of 〈110〉 NW, I on = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW. Ion increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.

AB - We successfully achieved the reduction of the parasitic resistance and the mobility enhancement in Si nanowire transistors (NW Tr.) by raised source/drain extensions with thin spacer (<10nm) and by stress induced from heavily-doped gate. Id variations are suppressed by the spacer thinning. By adopting 〈100〉 NW channel instead of 〈110〉 NW, I on = 1mA/μm for Ioff = 100nA/μm is achieved without stress techniques. Parasitic capacitance increase due to the spacer thinning is minimal. Heavily-doped poly-Si gate induces vertically compressive strain in NW. Ion increase of 43% is achieved by the additive strain effect of heavily-doped poly-Si gate and tensile stress liner.

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Source/drain and gate engineering on Si nanowire transistors with reduced parasitic resistance and strained silicon channel

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