Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits

Chika Tanaka; Masumi Saitoh; Kensuke Ota; Ken Uchida; Toshinori Numata

doi:10.1109/ESSDERC.2011.6044210

Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits

Chika Tanaka, Masumi Saitoh, Kensuke Ota, Ken Uchida, Toshinori Numata

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter is reduced 300 mV smaller than that of bulk-Tr.-based inverter due to the ideal sub-threshold slope. The performance benefits of NW-Tr.-based stacked circuit and SRAM cell are measured in terms of ultra-low voltage and ultra-low power operation.

Original language	English
Title of host publication	ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference
Pages	159-162
Number of pages	4
DOIs	https://doi.org/10.1109/ESSDERC.2011.6044210
Publication status	Published - 2011
Externally published	Yes
Event	41st European Solid-State Device Research Conference, ESSDERC 2011 - Helsinki, Finland Duration: 2011 Sept 12 → 2011 Sept 16

Publication series

Name	European Solid-State Device Research Conference
ISSN (Print)	1930-8876

Other

Other	41st European Solid-State Device Research Conference, ESSDERC 2011
Country/Territory	Finland
City	Helsinki
Period	11/9/12 → 11/9/16

ASJC Scopus subject areas

Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality

Access to Document

10.1109/ESSDERC.2011.6044210

Cite this

Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits. / Tanaka, Chika; Saitoh, Masumi; Ota, Kensuke et al.
ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference. 2011. p. 159-162 6044210 (European Solid-State Device Research Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Tanaka, C, Saitoh, M, Ota, K, Uchida, K & Numata, T 2011, Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits. in ESSDERC 2011 - Proceedings of the 41st European Solid-State Device Research Conference., 6044210, European Solid-State Device Research Conference, pp. 159-162, 41st European Solid-State Device Research Conference, ESSDERC 2011, Helsinki, Finland, 11/9/12. https://doi.org/10.1109/ESSDERC.2011.6044210

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abstract = "An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter is reduced 300 mV smaller than that of bulk-Tr.-based inverter due to the ideal sub-threshold slope. The performance benefits of NW-Tr.-based stacked circuit and SRAM cell are measured in terms of ultra-low voltage and ultra-low power operation.",

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AU - Numata, Toshinori

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AB - An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter is reduced 300 mV smaller than that of bulk-Tr.-based inverter due to the ideal sub-threshold slope. The performance benefits of NW-Tr.-based stacked circuit and SRAM cell are measured in terms of ultra-low voltage and ultra-low power operation.

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Spice-based performance analysis of ultra-low voltage Si nanowire CMOS circuits

Abstract

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ASJC Scopus subject areas

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