Stream applications on the dynamically reconfigurable processor

Masayasu Suzuki; Yohei Hasegawa; Yutaka Yamada; Naoto Kaneko; Katsuaki Deguchi; Hideharu Amano; Kenichiro Anjo; Masato Motomura; Kazutoshi Wakabayashi; Takao Toi; Toru Awashima

Stream applications on the dynamically reconfigurable processor

Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

35 Citations (Scopus)

Abstract

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

Original language	English
Title of host publication	Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04
Editors	O. Diessel, J. Williams
Pages	137-144
Number of pages	8
Publication status	Published - 2004 Dec 1
Event	2004 IEEE International Conference on Field-Programmable Technology, FPT '04 - Brisbane, Australia Duration: 2004 Dec 6 → 2004 Dec 8

Publication series

Name	Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04

Other

Other	2004 IEEE International Conference on Field-Programmable Technology, FPT '04
Country/Territory	Australia
City	Brisbane
Period	04/12/6 → 04/12/8

ASJC Scopus subject areas

Engineering(all)

Cite this

Suzuki, M., Hasegawa, Y., Yamada, Y., Kaneko, N., Deguchi, K., Amano, H., Anjo, K., Motomura, M., Wakabayashi, K., Toi, T., & Awashima, T. (2004). Stream applications on the dynamically reconfigurable processor. In O. Diessel, & J. Williams (Eds.), Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04 (pp. 137-144). (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

Stream applications on the dynamically reconfigurable processor. / Suzuki, Masayasu; Hasegawa, Yohei; Yamada, Yutaka et al.
Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. ed. / O. Diessel; J. Williams. 2004. p. 137-144 (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Suzuki, M, Hasegawa, Y, Yamada, Y, Kaneko, N, Deguchi, K, Amano, H, Anjo, K, Motomura, M, Wakabayashi, K, Toi, T & Awashima, T 2004, Stream applications on the dynamically reconfigurable processor. in O Diessel & J Williams (eds), Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04, pp. 137-144, 2004 IEEE International Conference on Field-Programmable Technology, FPT '04, Brisbane, Australia, 04/12/6.

Suzuki M, Hasegawa Y, Yamada Y, Kaneko N, Deguchi K, Amano H et al. Stream applications on the dynamically reconfigurable processor. In Diessel O, Williams J, editors, Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04. 2004. p. 137-144. (Proceedings - 2004 IEEE International Conference on Field-Programmable Technology, FPT '04).

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author = "Masayasu Suzuki and Yohei Hasegawa and Yutaka Yamada and Naoto Kaneko and Katsuaki Deguchi and Hideharu Amano and Kenichiro Anjo and Masato Motomura and Kazutoshi Wakabayashi and Takao Toi and Toru Awashima",

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AU - Suzuki, Masayasu

AU - Hasegawa, Yohei

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AU - Amano, Hideharu

AU - Anjo, Kenichiro

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AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on the DRP-1, the first prototype chip, and evaluation results are presented. By pipelining the executions, DRP-1 outperformed Pentium III/4, embedded CPU MIPS64, and Texas Instruments DSP TMS320C6713 in some stream application examples. We also present programming techniques applicable on dynamically reconfigurable processors and discuss their feasibility in boosting system performance.

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Stream applications on the dynamically reconfigurable processor

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