Stress and strain analysis using multi-physics solver for power device heat dissipation structures under thermal cycling test

Takahiro Asai; Masaaki Aoki; Akihiro Mochizuki; Takamitsu Honjo; Hitoshi Kida; Goro Yoshinari; Nobuhiko Nakano

doi:10.1109/ICEP-IAAC.2015.7111124

Stress and strain analysis using multi-physics solver for power device heat dissipation structures under thermal cycling test

Takahiro Asai, Masaaki Aoki, Akihiro Mochizuki, Takamitsu Honjo, Hitoshi Kida, Goro Yoshinari, Nobuhiko Nakano

Department of Electronics and Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

Power semiconductor device technology needs highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. This paper reports on 3D thermal stress profile and deformation with multi-physics solver for the system having Ag sintered bonding layer as a new chip attachment technology. The results clarified the reliability properties under thermal cycling test for Ag sintering chip attachment. It was found that the maximum stress value of Ag sintered bonding layer is lower than that of conventional solder layer, and the stress is concentrated at the upper edges for both Ag sintered and conventional solder bonding layers. DCB substrate model where the upper Cu layer thickness is thicker than the lower Cu layer thickness, showed the downward convex warp by the contraction difference between two Cu layers.

Original language	English
Title of host publication	ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	818-821
Number of pages	4
ISBN (Electronic)	9784904090138
DOIs	https://doi.org/10.1109/ICEP-IAAC.2015.7111124
Publication status	Published - 2015 May 20
Event	2015 International Conference on Electronic Packaging and iMAPS All Asia Conference, ICEP-IAAC 2015 - Kyoto, Japan Duration: 2015 Apr 14 → 2015 Apr 17

Publication series

Name	ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference

Other

Other	2015 International Conference on Electronic Packaging and iMAPS All Asia Conference, ICEP-IAAC 2015
Country/Territory	Japan
City	Kyoto
Period	15/4/14 → 15/4/17

Keywords

Ag sintering
chip attachment
multi-physics solver thermal cycling test
stress and strain analysis

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICEP-IAAC.2015.7111124

Cite this

Asai, T., Aoki, M., Mochizuki, A., Honjo, T., Kida, H., Yoshinari, G., & Nakano, N. (2015). Stress and strain analysis using multi-physics solver for power device heat dissipation structures under thermal cycling test. In ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (pp. 818-821). Article 7111124 (ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICEP-IAAC.2015.7111124

Stress and strain analysis using multi-physics solver for power device heat dissipation structures under thermal cycling test. / Asai, Takahiro; Aoki, Masaaki; Mochizuki, Akihiro et al.
ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference. Institute of Electrical and Electronics Engineers Inc., 2015. p. 818-821 7111124 (ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Asai, T, Aoki, M, Mochizuki, A, Honjo, T, Kida, H, Yoshinari, G & Nakano, N 2015, Stress and strain analysis using multi-physics solver for power device heat dissipation structures under thermal cycling test. in ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference., 7111124, ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference, Institute of Electrical and Electronics Engineers Inc., pp. 818-821, 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference, ICEP-IAAC 2015, Kyoto, Japan, 15/4/14. https://doi.org/10.1109/ICEP-IAAC.2015.7111124

Asai T, Aoki M, Mochizuki A, Honjo T, Kida H, Yoshinari G et al. Stress and strain analysis using multi-physics solver for power device heat dissipation structures under thermal cycling test. In ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference. Institute of Electrical and Electronics Engineers Inc. 2015. p. 818-821. 7111124. (ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference). doi: 10.1109/ICEP-IAAC.2015.7111124

Asai, Takahiro ; Aoki, Masaaki ; Mochizuki, Akihiro et al. / Stress and strain analysis using multi-physics solver for power device heat dissipation structures under thermal cycling test. ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference. Institute of Electrical and Electronics Engineers Inc., 2015. pp. 818-821 (ICEP-IAAC 2015 - 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference).

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abstract = "Power semiconductor device technology needs highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. This paper reports on 3D thermal stress profile and deformation with multi-physics solver for the system having Ag sintered bonding layer as a new chip attachment technology. The results clarified the reliability properties under thermal cycling test for Ag sintering chip attachment. It was found that the maximum stress value of Ag sintered bonding layer is lower than that of conventional solder layer, and the stress is concentrated at the upper edges for both Ag sintered and conventional solder bonding layers. DCB substrate model where the upper Cu layer thickness is thicker than the lower Cu layer thickness, showed the downward convex warp by the contraction difference between two Cu layers.",

keywords = "Ag sintering, chip attachment, multi-physics solver thermal cycling test, stress and strain analysis",

author = "Takahiro Asai and Masaaki Aoki and Akihiro Mochizuki and Takamitsu Honjo and Hitoshi Kida and Goro Yoshinari and Nobuhiko Nakano",

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AU - Asai, Takahiro

AU - Aoki, Masaaki

AU - Mochizuki, Akihiro

AU - Honjo, Takamitsu

AU - Kida, Hitoshi

AU - Yoshinari, Goro

AU - Nakano, Nobuhiko

PY - 2015/5/20

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N2 - Power semiconductor device technology needs highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. This paper reports on 3D thermal stress profile and deformation with multi-physics solver for the system having Ag sintered bonding layer as a new chip attachment technology. The results clarified the reliability properties under thermal cycling test for Ag sintering chip attachment. It was found that the maximum stress value of Ag sintered bonding layer is lower than that of conventional solder layer, and the stress is concentrated at the upper edges for both Ag sintered and conventional solder bonding layers. DCB substrate model where the upper Cu layer thickness is thicker than the lower Cu layer thickness, showed the downward convex warp by the contraction difference between two Cu layers.

AB - Power semiconductor device technology needs highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. This paper reports on 3D thermal stress profile and deformation with multi-physics solver for the system having Ag sintered bonding layer as a new chip attachment technology. The results clarified the reliability properties under thermal cycling test for Ag sintering chip attachment. It was found that the maximum stress value of Ag sintered bonding layer is lower than that of conventional solder layer, and the stress is concentrated at the upper edges for both Ag sintered and conventional solder bonding layers. DCB substrate model where the upper Cu layer thickness is thicker than the lower Cu layer thickness, showed the downward convex warp by the contraction difference between two Cu layers.

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Stress and strain analysis using multi-physics solver for power device heat dissipation structures under thermal cycling test

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