TY - GEN
T1 - Superpixel accelerator for computer vision applications on arria 10 SoC
AU - Akagic, Amila
AU - Buza, Emir
AU - Turcinhodzic, Razija
AU - Haseljic, Hana
AU - Hiroyuki, Noda
AU - Amano, Hideharu
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/11
Y1 - 2018/7/11
N2 - Superpixel segmentation is a very popular image segmentation technique used in various computer vision tasks. Recently, a number of superpixel algorithms have been proposed in literature. One such algorithm is considered as the-state-of-the-art in superpixel segmentation: Simple Linear Iterative Clustering or SLIC. However, its original implementation has a long execution time on high performance processors designed within the common mobile and enterprise applications, as well on high-end processors such as Intel Xeon. Overall, the execution time for single-threaded implementation is considered critical for real-time or near real-time applications. In this paper, we explore the possibility of accelerating parts of the SLIC image segmentation critical for performance, by designing the image segmentation accelerator for Intel's Arria 10 SoC. We propose a novel architecture to enable hardware acceleration by addressing the problem of hardware/software partitioning to minimize the overall program latency.
AB - Superpixel segmentation is a very popular image segmentation technique used in various computer vision tasks. Recently, a number of superpixel algorithms have been proposed in literature. One such algorithm is considered as the-state-of-the-art in superpixel segmentation: Simple Linear Iterative Clustering or SLIC. However, its original implementation has a long execution time on high performance processors designed within the common mobile and enterprise applications, as well on high-end processors such as Intel Xeon. Overall, the execution time for single-threaded implementation is considered critical for real-time or near real-time applications. In this paper, we explore the possibility of accelerating parts of the SLIC image segmentation critical for performance, by designing the image segmentation accelerator for Intel's Arria 10 SoC. We propose a novel architecture to enable hardware acceleration by addressing the problem of hardware/software partitioning to minimize the overall program latency.
KW - Computer Vision
KW - Hardware Acceleration
KW - Image segmentation
KW - OpenCL
UR - http://www.scopus.com/inward/record.url?scp=85050959988&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85050959988&partnerID=8YFLogxK
U2 - 10.1109/DDECS.2018.00-12
DO - 10.1109/DDECS.2018.00-12
M3 - Conference contribution
AN - SCOPUS:85050959988
T3 - Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018
SP - 55
EP - 60
BT - Proceedings - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2018
Y2 - 25 April 2018 through 27 April 2018
ER -