Symbol-rate clock recovery for integrating DFE receivers

Tsutomu Takeya; Tadahiro Kuroda

doi:10.1587/transfun.E96.A.705

Symbol-rate clock recovery for integrating DFE receivers

Tsutomu Takeya, Tadahiro Kuroda

Research output: Contribution to journal › Article › peer-review

Abstract

In this paper, a symbol-rate clock recovery scheme for a receiver that uses an integrating decision feedback equalizer (DFE) is proposed. The proposed clock recovery using expected received signal amplitudes as the criterion realizes minimum mean square error (MMSE) clock recovery. A receiver architecture using an integrating DFE with the proposed symbol-rate clock recovery is also proposed. The proposed clock recovery algorithm successfully recovered the clock phase in a system level simulation only with a DFE. Higher jitter tolerance than 0.26 UI_PP at 10 Gb/s operation was also confirmed in the simulation with an 11 dB channel loss at 5 GHz.

Original language	English
Pages (from-to)	705-712
Number of pages	8
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E96-A
Issue number	3
DOIs	https://doi.org/10.1587/transfun.E96.A.705
Publication status	Published - 2013 Mar

Keywords

Clock recovery
Decision feedback equalizer (DFE)
Integrating DFE
Receiver architecture
Serial link

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

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10.1587/transfun.E96.A.705

Cite this

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Symbol-rate clock recovery for integrating DFE receivers

Abstract

Keywords

ASJC Scopus subject areas

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