TY - GEN
T1 - SystemVerilog assertion for microarchitecture education considering situated nature of learning
T2 - 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011
AU - Takahashi, Ryuichi
AU - Takefuji, Yoshiyasu
PY - 2011/8/10
Y1 - 2011/8/10
N2 - SystemVerilog assertion (SVA) is a way to express properties that are expected to be true in a design described in Verilog HDL IEEE1364 standard. We have already reported that legitimate peripheral participation (LPP) works very well for the fine grain microprocessor design education on FPGA where the heart of the system is chosen as the way-in which is the first step for the observation in LPP. We have demonstrated its effectiveness on superscalar design education, while the prior pipeline design education failed. The failure was caused by the top down design methodology guided in the education for the pipelining which appeared to be too difficult. Appropriate scheme to observe the heart of the pipelining is needed. We have found that SVA plays a key role where two senior students succeeded to design pipelined RISC having 3 stages and pipelined CISC having 4 stages in 2 months. White box test by using SVA enables the two senior students to observe the heart of the pipelining very effectively.
AB - SystemVerilog assertion (SVA) is a way to express properties that are expected to be true in a design described in Verilog HDL IEEE1364 standard. We have already reported that legitimate peripheral participation (LPP) works very well for the fine grain microprocessor design education on FPGA where the heart of the system is chosen as the way-in which is the first step for the observation in LPP. We have demonstrated its effectiveness on superscalar design education, while the prior pipeline design education failed. The failure was caused by the top down design methodology guided in the education for the pipelining which appeared to be too difficult. Appropriate scheme to observe the heart of the pipelining is needed. We have found that SVA plays a key role where two senior students succeeded to design pipelined RISC having 3 stages and pipelined CISC having 4 stages in 2 months. White box test by using SVA enables the two senior students to observe the heart of the pipelining very effectively.
KW - Assertion
KW - Legitimate peripheral participation
KW - Microarchitecture education
KW - Ppipelining
KW - SystemVerilog
UR - http://www.scopus.com/inward/record.url?scp=79961130604&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=79961130604&partnerID=8YFLogxK
U2 - 10.1109/MSE.2011.5937107
DO - 10.1109/MSE.2011.5937107
M3 - Conference contribution
AN - SCOPUS:79961130604
SN - 9781457705489
T3 - 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011
SP - 112
EP - 113
BT - 2011 IEEE International Conference on Microelectronic Systems Education, MSE 2011
Y2 - 5 June 2011 through 6 June 2011
ER -