@inproceedings{77f4e9df75bc48f682eb6f12037fc66b,
title = "TCI Tester: Tester for through Chip Interface",
keywords = "Wireless inter-chip communicaton, TCI",
author = "Hideto Kayashima and Hideharu Amano",
note = "Funding Information: This study was supported by JSPS KAKENHI (B) 18H03215 Building Block Computing System with a chip-bridge stacking scheme. The chip design was performed by the University of Tokyo Large Scale Integrated System Design Education and Research Center (VDEC) using Synopsys, Cadence, and Mentor CAD.; 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021 ; Conference date: 18-01-2021 Through 21-01-2021",
year = "2021",
month = jan,
day = "18",
doi = "10.1145/3394885.3431660",
language = "English",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "103--104",
booktitle = "Proceedings of the 26th Asia and South Pacific Design Automation Conference, ASP-DAC 2021",
}