Threshold voltage shift and drain current degradation by NBT stress in Si (110) pMOSFETs

Kensuke Ota, Masumi Saitoh, Yukio Nakabayashi, Takamitsu Ishihara, Toshinori Numata, Ken Uchida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Threshold voltage shift and drain current degradation by NBT stress in Si (100) and (110) pMOSFETs are systematically studied. Threshold voltage shift in (110) pFET is larger than that in (100) pFET. However, time and temperature dependence of NBTI suggest that the mechanisms of the NBTI degradation are independent of the surface orientations. It is newly found that the drain current degradation in (110) pFET is severer than that in (100) pFET even when the same amount of charges at the interface is generated. This can be explained by larger mobility degradation in (110) pFETs due to the generated interface traps.

Original languageEnglish
Title of host publication2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010
Pages134-137
Number of pages4
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 European Solid State Device Research Conference, ESSDERC 2010 - Sevilla, Spain
Duration: 2010 Sept 142010 Sept 16

Publication series

Name2010 Proceedings of the European Solid State Device Research Conference, ESSDERC 2010

Other

Other2010 European Solid State Device Research Conference, ESSDERC 2010
Country/TerritorySpain
CitySevilla
Period10/9/1410/9/16

ASJC Scopus subject areas

  • Condensed Matter Physics

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