Through chip interface based three-dimensional FPGA architecture exploration

Li Chung Hsu, Masato Motomura, Yasuhiro Take, Tadahiro Kuroda

    Research output: Contribution to journalArticlepeer-review


    This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.

    Original languageEnglish
    Pages (from-to)288-297
    Number of pages10
    JournalIEICE Transactions on Electronics
    Issue number4
    Publication statusPublished - 2015 Apr 1


    • 3-DFPGA
    • FPGA
    • TCI
    • TPR
    • TSV
    • ThruChip
    • VPR

    ASJC Scopus subject areas

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering


    Dive into the research topics of 'Through chip interface based three-dimensional FPGA architecture exploration'. Together they form a unique fingerprint.

    Cite this