Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Takao Toi; Toru Awashima; Masato Motomura; Hideharu Amano

doi:10.1109/MWSCAS.2011.6026300

Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Takao Toi, Toru Awashima, Masato Motomura, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Citations (Scopus)

Abstract

This paper presents our dynamically reconfigurable processor (DRP) and its compiler. We first introduce our DRP architecture, which is suitable for both parallelizable and control-intensive code segments since it has a stand-alone finite state machine that switches "contexts" consisting of many processing elements (PEs). Then, some optimization techniques used in the compiler are explained, such as a loop pipelining, iterative synthesis technique to shorten wire delay, and a technique to achieve higher area efficiency by utilizing the benefit of having multiple contexts. Lastly, two products are shown as application examples.

Original language	English
Title of host publication	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs	https://doi.org/10.1109/MWSCAS.2011.6026300
Publication status	Published - 2011 Oct 13
Event	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of Duration: 2011 Aug 7 → 2011 Aug 10

Publication series

Name	Midwest Symposium on Circuits and Systems
ISSN (Print)	1548-3746

Other

Other	54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
Country/Territory	Korea, Republic of
City	Seoul
Period	11/8/7 → 11/8/10

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/MWSCAS.2011.6026300

Cite this

Time and space-multiplexed compilation challenges for dynamically reconfigurable processors. / Toi, Takao; Awashima, Toru; Motomura, Masato et al.
54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026300 (Midwest Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Toi, T, Awashima, T, Motomura, M & Amano, H 2011, Time and space-multiplexed compilation challenges for dynamically reconfigurable processors. in 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026300, Midwest Symposium on Circuits and Systems, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 11/8/7. https://doi.org/10.1109/MWSCAS.2011.6026300

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AB - This paper presents our dynamically reconfigurable processor (DRP) and its compiler. We first introduce our DRP architecture, which is suitable for both parallelizable and control-intensive code segments since it has a stand-alone finite state machine that switches "contexts" consisting of many processing elements (PEs). Then, some optimization techniques used in the compiler are explained, such as a loop pipelining, iterative synthesis technique to shorten wire delay, and a technique to achieve higher area efficiency by utilizing the benefit of having multiple contexts. Lastly, two products are shown as application examples.

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Time and space-multiplexed compilation challenges for dynamically reconfigurable processors

Abstract

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