Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Yohei Hasegawa; Shohei Abe; Katsuaki Deguchi; Masayasu Suzuki; Hideharu Amano

Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano

Department of Information and Computer Science

Research output: Contribution to conference › Paper › peer-review

Abstract

Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.

Original language	English
Number of pages	1
Publication status	Published - 2005 Jun 20
Event	ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005 - Monterey, CA, United States Duration: 2005 Feb 20 → 2005 Feb 22

Conference

Conference	ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005
Country/Territory	United States
City	Monterey, CA
Period	05/2/20 → 05/2/22

ASJC Scopus subject areas

Computer Science(all)

Cite this

Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation. / Hasegawa, Yohei; Abe, Shohei; Deguchi, Katsuaki et al.
2005. Paper presented at ACM/SIGDA Thirteenth ACM International Symposium on Field Programmable Gate Arrays - FPGA 2005, Monterey, CA, United States.

Research output: Contribution to conference › Paper › peer-review

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AU - Hasegawa, Yohei

AU - Abe, Shohei

AU - Deguchi, Katsuaki

AU - Suzuki, Masayasu

AU - Amano, Hideharu

PY - 2005/6/20

Y1 - 2005/6/20

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AB - Dynamically Reconfigurable Processor (DRP) developed by NEC Electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. The impact of time-multiplexed execution to performance and cost is analyzed based on real designs including an IPsec router. The Parallelism Diagram which shows the required PEs in each step of the algorithm is introduced as the basis of the analysis, and models for performance and cost are shown. Evaluation results show that the time-multiplexed execution improves the performance per cost around 4.5 to 14 times than that of the case without time-multiplexed execution.

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M3 - Paper

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Time-multiplexed execution on the dynamically reconfigurable processor - A performance/cost evaluation

Abstract

Conference

ASJC Scopus subject areas

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