TORUS-switch: A scalable internal speed-up ATM switch architecture and its 5 Gbit/s switch LSI

K. Genda; N. Yamanaka

doi:10.1049/el:19950578

TORUS-switch: A scalable internal speed-up ATM switch architecture and its 5 Gbit/s switch LSI

K. Genda, N. Yamanaka

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient.

Original language	English
Pages (from-to)	906-908
Number of pages	3
Journal	Electronics Letters
Volume	31
Issue number	11
DOIs	https://doi.org/10.1049/el:19950578
Publication status	Published - 1995 May 25
Externally published	Yes

Keywords

Asynchronous transfer mode. Switches

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1049/el:19950578

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abstract = "A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient.",

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T2 - A scalable internal speed-up ATM switch architecture and its 5 Gbit/s switch LSI

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AU - Yamanaka, N.

PY - 1995/5/25

Y1 - 1995/5/25

N2 - A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient.

AB - A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient.

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TORUS-switch: A scalable internal speed-up ATM switch architecture and its 5 Gbit/s switch LSI

Abstract

Keywords

ASJC Scopus subject areas

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