Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Weihan Wang; Yuya Ohta; Yoshifumi Ishii; Kimiyoshi Usami; Hideharu Amano

doi:10.1109/COOLChips.2012.6216587

Trade-off analysis of fine-grained power gating methods for functional units in a CPU

Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

High-speed power gating (PG) techniques are useful for reducing leakage power of functional units in a CPU core. This paper analyzes trade off of functional units in a MIPS R3000 based processor with three fine-grained PG methods: the cell-based, row-based and ring-based. Compared with the cell-based PG technique, which was used in our previous work - Geyser-1 processor, the row-based and ring-based PG technique achieved much smaller area and less implemental cost with a certain additional delay to wake-up latency. The simulation results with benchmark programs show that all three methods can reduce leakage power by 28∼54% at 25C.

Original language	English
Title of host publication	Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV
DOIs	https://doi.org/10.1109/COOLChips.2012.6216587
Publication status	Published - 2012 Jul 25
Event	15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV - Yokohama, Japan Duration: 2012 Apr 18 → 2012 Apr 20

Publication series

Name	Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV

Other

Other	15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV
Country/Territory	Japan
City	Yokohama
Period	12/4/18 → 12/4/20

Keywords

Leakage Power and Processor
Power Gating

ASJC Scopus subject areas

Computer Networks and Communications

Access to Document

10.1109/COOLChips.2012.6216587

Cite this

Wang, W., Ohta, Y., Ishii, Y., Usami, K., & Amano, H. (2012). Trade-off analysis of fine-grained power gating methods for functional units in a CPU. In Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV Article 6216587 (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV). https://doi.org/10.1109/COOLChips.2012.6216587

Trade-off analysis of fine-grained power gating methods for functional units in a CPU. / Wang, Weihan; Ohta, Yuya; Ishii, Yoshifumi et al.
Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV. 2012. 6216587 (Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Wang, W, Ohta, Y, Ishii, Y, Usami, K & Amano, H 2012, Trade-off analysis of fine-grained power gating methods for functional units in a CPU. in Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV., 6216587, Symposium on Low-Power and High-Speed Chips - Proceedings for 2012 IEEE COOL Chips XV, 15th IEEE Symposium on Low-Powerand High-Speed Chips, COOL Chips XV, Yokohama, Japan, 12/4/18. https://doi.org/10.1109/COOLChips.2012.6216587

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Trade-off analysis of fine-grained power gating methods for functional units in a CPU

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