Abstract
This paper proposes a software/hardware co-design system for a Trax solver. Since development with Hardware Description Language (HDL) is tough work, we selected an approach: 1. writing C++ code, 2. finding bottleneck of the problem, and 3. re-writing the bottleneck part in the High Level Synthesis(HLS). Generally, game AI algorithm is divided into 3 parts, data structure, searching, and board evaluation. In this design, we focused on the data structure and implemented an incremental update algorithm. As a result, we can detect a line and an attack with O(1). Also, we implemented a local pruning, which reduces search area when the search depth becomes large in alpha beta tree search. The implemented solver works with 150MHz clock on Xilinx XC7Z020-CLG484 of Digilent ZedBoard.
Original language | English |
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Title of host publication | Proceedings of the 2016 International Conference on Field-Programmable Technology, FPT 2016 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 323-326 |
Number of pages | 4 |
ISBN (Electronic) | 9781509056026 |
DOIs | |
Publication status | Published - 2017 May 15 |
Event | 15th International Conference on Field-Programmable Technology, FPT 2016 - Xi'an, China Duration: 2016 Dec 7 → 2016 Dec 9 |
Other
Other | 15th International Conference on Field-Programmable Technology, FPT 2016 |
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Country/Territory | China |
City | Xi'an |
Period | 16/12/7 → 16/12/9 |
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering
- Safety, Risk, Reliability and Quality
- Instrumentation
- Hardware and Architecture