Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Kimiyoshi Usami; Makoto Miyauchi; Masaru Kudo; Kazumitsu Takagi; Hideharu Amano; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura

doi:10.1109/ISSOC.2014.6972438

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Kimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura

Department of Information and Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation.

Original language	English
Title of host publication	2014 International Symposium on System-on-Chip, SoC 2014
Editors	Jari Nurmi, Peeter Ellervee, Dragomir Milojevic, Ondrej Daniel, Tommi Paakki
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479968909
DOIs	https://doi.org/10.1109/ISSOC.2014.6972438
Publication status	Published - 2014 Dec 2
Event	2014 16th International Symposium on System-on-Chip, SoC 2014 - Tampere, Finland Duration: 2014 Oct 28 → 2014 Oct 29

Publication series

Name	2014 International Symposium on System-on-Chip, SoC 2014

Other

Other	2014 16th International Symposium on System-on-Chip, SoC 2014
Country/Territory	Finland
City	Tampere
Period	14/10/28 → 14/10/29

Keywords

ground bounce
low power
power gating

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/ISSOC.2014.6972438

Cite this

Usami, K., Miyauchi, M., Kudo, M., Takagi, K., Amano, H., Namiki, M., Kondo, M., & Nakamura, H. (2014). Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. In J. Nurmi, P. Ellervee, D. Milojevic, O. Daniel, & T. Paakki (Eds.), 2014 International Symposium on System-on-Chip, SoC 2014 Article 6972438 (2014 International Symposium on System-on-Chip, SoC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSOC.2014.6972438

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. / Usami, Kimiyoshi; Miyauchi, Makoto; Kudo, Masaru et al.
2014 International Symposium on System-on-Chip, SoC 2014. ed. / Jari Nurmi; Peeter Ellervee; Dragomir Milojevic; Ondrej Daniel; Tommi Paakki. Institute of Electrical and Electronics Engineers Inc., 2014. 6972438 (2014 International Symposium on System-on-Chip, SoC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Usami, K, Miyauchi, M, Kudo, M, Takagi, K, Amano, H, Namiki, M, Kondo, M & Nakamura, H 2014, Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. in J Nurmi, P Ellervee, D Milojevic, O Daniel & T Paakki (eds), 2014 International Symposium on System-on-Chip, SoC 2014., 6972438, 2014 International Symposium on System-on-Chip, SoC 2014, Institute of Electrical and Electronics Engineers Inc., 2014 16th International Symposium on System-on-Chip, SoC 2014, Tampere, Finland, 14/10/28. https://doi.org/10.1109/ISSOC.2014.6972438

Usami K, Miyauchi M, Kudo M, Takagi K, Amano H, Namiki M et al. Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. In Nurmi J, Ellervee P, Milojevic D, Daniel O, Paakki T, editors, 2014 International Symposium on System-on-Chip, SoC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6972438. (2014 International Symposium on System-on-Chip, SoC 2014). doi: 10.1109/ISSOC.2014.6972438

Usami, Kimiyoshi ; Miyauchi, Makoto ; Kudo, Masaru et al. / Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. 2014 International Symposium on System-on-Chip, SoC 2014. editor / Jari Nurmi ; Peeter Ellervee ; Dragomir Milojevic ; Ondrej Daniel ; Tommi Paakki. Institute of Electrical and Electronics Engineers Inc., 2014. (2014 International Symposium on System-on-Chip, SoC 2014).

@inproceedings{f23f814018014888af49b50fad5ab9ac,

title = "Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating",

abstract = "This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation.",

keywords = "ground bounce, low power, power gating",

author = "Kimiyoshi Usami and Makoto Miyauchi and Masaru Kudo and Kazumitsu Takagi and Hideharu Amano and Mitaro Namiki and Masaaki Kondo and Hiroshi Nakamura",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 2014 16th International Symposium on System-on-Chip, SoC 2014 ; Conference date: 28-10-2014 Through 29-10-2014",

year = "2014",

month = dec,

day = "2",

doi = "10.1109/ISSOC.2014.6972438",

language = "English",

series = "2014 International Symposium on System-on-Chip, SoC 2014",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

editor = "Jari Nurmi and Peeter Ellervee and Dragomir Milojevic and Ondrej Daniel and Tommi Paakki",

booktitle = "2014 International Symposium on System-on-Chip, SoC 2014",

}

TY - GEN

T1 - Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

AU - Usami, Kimiyoshi

AU - Miyauchi, Makoto

AU - Kudo, Masaru

AU - Takagi, Kazumitsu

AU - Amano, Hideharu

AU - Namiki, Mitaro

AU - Kondo, Masaaki

AU - Nakamura, Hiroshi

PY - 2014/12/2

Y1 - 2014/12/2

N2 - This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation.

AB - This paper describes a new approach to reduce the ground bounce (GB) while keeping the wakeup time short for fine-grain power gating. We propose a novel algorithm to synthesize an optimal unbalanced buffer tree (UBT) that turns on parallel power switches with slight time differences. We have applied our algorithm to function units of a 32-bit microprocessor. Experimental results have revealed that our UBT gives better solution than the conventional daisy-chain approach in the space of wakeup time and GB. For example, in the ALU, our UBT suppressed the maximum GB voltage to 16mV which is 24% smaller than that of the parallel daisy chain, while keeping the wakeup time 0.6ns. In the 32b×32b multiplier, our UBT suppressed GB by 32% lower than the daisy chain but still kept the wakeup time 0.7ns. The microprocessor test chip with our UBT technique is successfully under operation.

KW - ground bounce

KW - low power

KW - power gating

UR - http://www.scopus.com/inward/record.url?scp=84919363461&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84919363461&partnerID=8YFLogxK

U2 - 10.1109/ISSOC.2014.6972438

DO - 10.1109/ISSOC.2014.6972438

M3 - Conference contribution

AN - SCOPUS:84919363461

T3 - 2014 International Symposium on System-on-Chip, SoC 2014

BT - 2014 International Symposium on System-on-Chip, SoC 2014

A2 - Nurmi, Jari

A2 - Ellervee, Peeter

A2 - Milojevic, Dragomir

A2 - Daniel, Ondrej

A2 - Paakki, Tommi

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2014 16th International Symposium on System-on-Chip, SoC 2014

Y2 - 28 October 2014 through 29 October 2014

ER -

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating

Abstract

Publication series

Other

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this