Utilizing surplus timing for power reduction

Mototsugu Hamada, Yukio Ootaguro, Tadahiro Kuroda

    Research output: Contribution to journalArticlepeer-review

    59 Citations (Scopus)


    Multiple Vdd's, multiple Vth's, and multiple transistor width for utilizing surplus timing in non-critical paths for power reduction is investigated. Theoretical models are developed from which rules of thumb for optimum Vdd's, Vth's, and W's are derived, as well as knowledge for future design.

    Original languageEnglish
    Pages (from-to)89-92
    Number of pages4
    JournalProceedings of the Custom Integrated Circuits Conference
    Publication statusPublished - 2001 Jan 1

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering


    Dive into the research topics of 'Utilizing surplus timing for power reduction'. Together they form a unique fingerprint.

    Cite this