Variable supply-voltage scheme for low-power high-speed CMOS digital design

Tadahiro Kuroda; Kojiro Suzuki; Shinji Mita; Tetsuya Fujita; Fumiyuki Yamane; Fumihiko Sano; Akihiko Chiba; Yoshinori Watanabe; Koji Matsuda; Takeo Maeda; Takayasu Sakurai; Tohru Furuyama

doi:10.1109/4.661211

Variable supply-voltage scheme for low-power high-speed CMOS digital design

Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama

Research output: Contribution to journal › Article › peer-review

204 Citations (Scopus)

Abstract

This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supply voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

Original language	English
Pages (from-to)	454-461
Number of pages	8
Journal	IEEE Journal of Solid-State Circuits
Volume	33
Issue number	3
DOIs	https://doi.org/10.1109/4.661211
Publication status	Published - 1998 Mar
Externally published	Yes

Keywords

Buck converter
Low power CMOS circuits
Low threshold voltage
Low voltage

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/4.661211

Cite this

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abstract = "This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supply voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.",

keywords = "Buck converter, Low power CMOS circuits, Low threshold voltage, Low voltage",

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T1 - Variable supply-voltage scheme for low-power high-speed CMOS digital design

AU - Kuroda, Tadahiro

AU - Suzuki, Kojiro

AU - Mita, Shinji

AU - Fujita, Tetsuya

AU - Yamane, Fumiyuki

AU - Sano, Fumihiko

AU - Chiba, Akihiko

AU - Watanabe, Yoshinori

AU - Matsuda, Koji

AU - Maeda, Takeo

AU - Sakurai, Takayasu

AU - Furuyama, Tohru

PY - 1998/3

Y1 - 1998/3

N2 - This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supply voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

AB - This paper describes a variable supply-voltage (VS) scheme. From an external supply, the VS scheme automatically generates minimum internal supply voltages by feedback control of a buck converter, a speed detector, and a timing controller so that they meet the demand on its operation frequency. A 32-b RISC core processor is developed in a 0.4-μm CMOS technology which optimally controls the internal supply voltages with the VS scheme and the threshold voltages through substrate bias control. Performance in MIPS/W is improved by a factor of more than two compared with its conventional CMOS design.

KW - Buck converter

KW - Low power CMOS circuits

KW - Low threshold voltage

KW - Low voltage

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Variable supply-voltage scheme for low-power high-speed CMOS digital design

Abstract

Keywords

ASJC Scopus subject areas

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