Abstract
A variable supply-voltage (VS) scheme with a high power-conversion-efficiency DC-DC converter is presented. A new pulse width modulation (PWM) circuit for the DC-DC converter is proposed to reduce both of power consumption and chip area. The power conversion efficiency reaches up to 95%, and the area is less than half of the conventional design. The VS scheme contains critical path replica circuits of an MPEG-4 codec LSI, and its output voltage is controlled by monitoring delay time of the replica circuits. Consequently the VS scheme can automatically generate minimal internal supply voltage that meets the demand from the operation frequency of an MPEG-4 codec LSI. The advantages of this circuit are successfully demonstrated through fabrication of a test chip using a 0.3 μm CMOS technology.
| Original language | English |
|---|---|
| Pages | 54-59 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 1999 |
| Externally published | Yes |
| Event | Proceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED) - San Diego, CA, USA Duration: 1999 Aug 16 → 1999 Aug 17 |
Other
| Other | Proceedings of the 1999 International Conference on Low Power Electronics and Design (ISLPED) |
|---|---|
| City | San Diego, CA, USA |
| Period | 99/8/16 → 99/8/17 |
ASJC Scopus subject areas
- Engineering(all)