Virtual core based synthesis of SoC architectures

Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada

Research output: Chapter in Book/Report/Conference proceedingConference contribution


The reuse of high-level design intellectual properties is indispensable to reduce SoC design time. It has been difficult for SoC designers to design and compare two or more SoC architectures in a given product design time. In this paper, we present a synthesis methodology of SoC architectures using Virtual Cores (VCores) to perform architectural explorations in a short period. The proposed synthesis methodology generates an initial architecture, which consists of a CPU, buses, I/Os. etc., and makes tradeoffs between hardware and software on mapped software VCores and hardware VCores models. The authors show the usefulness of me proposed method from the results of an architecture level design experiment.

Original languageEnglish
Title of host publicationASICON 2003 - 2003 5th International Conference on ASIC, Proceedings
EditorsTing-Ao Tang, Wenhong Li, Huihua Yu
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Electronic)078037889X
Publication statusPublished - 2003
Externally publishedYes
Event5th International Conference on ASIC, ASICON 2003 - Beijing, China
Duration: 2003 Oct 212003 Oct 24

Publication series

NameIEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
ISSN (Print)1523-553X


Conference5th International Conference on ASIC, ASICON 2003

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Engineering(all)
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering


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