TY - GEN
T1 - Virtual core based synthesis of SoC architectures
AU - Nishi, Hiroaki
AU - Muraoka, Michiaki
AU - Morizawa, Rafael K.
AU - Yokota, Hideaki
AU - Hamada, Hideyuki
N1 - Funding Information:
This work was sponsored by NEDO (New Energy and Industrial Technology Development Organization) as "SoC Advanced Design Technology Development Project" (VCDS Project).
Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - The reuse of high-level design intellectual properties is indispensable to reduce SoC design time. It has been difficult for SoC designers to design and compare two or more SoC architectures in a given product design time. In this paper, we present a synthesis methodology of SoC architectures using Virtual Cores (VCores) to perform architectural explorations in a short period. The proposed synthesis methodology generates an initial architecture, which consists of a CPU, buses, I/Os. etc., and makes tradeoffs between hardware and software on mapped software VCores and hardware VCores models. The authors show the usefulness of me proposed method from the results of an architecture level design experiment.
AB - The reuse of high-level design intellectual properties is indispensable to reduce SoC design time. It has been difficult for SoC designers to design and compare two or more SoC architectures in a given product design time. In this paper, we present a synthesis methodology of SoC architectures using Virtual Cores (VCores) to perform architectural explorations in a short period. The proposed synthesis methodology generates an initial architecture, which consists of a CPU, buses, I/Os. etc., and makes tradeoffs between hardware and software on mapped software VCores and hardware VCores models. The authors show the usefulness of me proposed method from the results of an architecture level design experiment.
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U2 - 10.1109/ICASIC.2003.1277485
DO - 10.1109/ICASIC.2003.1277485
M3 - Conference contribution
AN - SCOPUS:85085506171
T3 - IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings
SP - 35
EP - 40
BT - ASICON 2003 - 2003 5th International Conference on ASIC, Proceedings
A2 - Tang, Ting-Ao
A2 - Li, Wenhong
A2 - Yu, Huihua
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th International Conference on ASIC, ASICON 2003
Y2 - 21 October 2003 through 24 October 2003
ER -