TY - GEN
T1 - Wire congestion aware synthesis for a dynamically reconfigurable processor
AU - Toi, Takao
AU - Okamoto, Takumi
AU - Awashima, Toru
AU - Wakabayashi, Kazutoshi
AU - Amano, Hideharu
PY - 2010/12/1
Y1 - 2010/12/1
N2 - This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.
AB - This paper presents two iterative synthesis techniques between a high-level synthesizer (HLS) and the place and route tool to shorten the prolonged wire delay for a dynamically reconfigurable processor. At first, we use feedback wire delays for each context to a scheduler in the HLS. The experimental results showed that a critical-path delay was shorten 21% on average for applications with timing closure problems. Second, we skip the routing and estimate wire delays based on their congestions. The synthesis time was cut by 1/3 with only four points down on delay improvement rate.
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U2 - 10.1109/FPT.2010.5681481
DO - 10.1109/FPT.2010.5681481
M3 - Conference contribution
AN - SCOPUS:79551532395
SN - 9781424489817
T3 - Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
SP - 300
EP - 303
BT - Proceedings - 2010 International Conference on Field-Programmable Technology, FPT'10
T2 - 2010 International Conference on Field-Programmable Technology, FPT'10
Y2 - 8 December 2010 through 10 December 2010
ER -