0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

M. Nomura; A. Muramatsu; H. Takeno; S. Hattori; D. Ogawa; M. Nasu; K. Hirairi; S. Kumashiro; S. Moriwaki; Y. Yamamoto; S. Miyano; Y. Hiraku; I. Hayashi; K. Yoshioka; A. Shikata; H. Ishikuro; M. Ahn; Y. Okuma; X. Zhang; Y. Ryu; K. Ishida; M. Takamiya; T. Kuroda; H. Shinohara; T. Sakurai

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS

M. Nomura
, A. Muramatsu
, H. Takeno
, S. Hattori
, D. Ogawa
, M. Nasu
, K. Hirairi
, S. Kumashiro
, S. Moriwaki
, Y. Yamamoto
, S. Miyano
, Y. Hiraku
, I. Hayashi
, K. Yoshioka
, A. Shikata
, H. Ishikuro
, M. Ahn
, Y. Okuma
, X. Zhang
, Y. Ryu

K. Ishida, M. Takamiya, T. Kuroda, H. Shinohara, T. Sakurai

電気情報工学科

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

本文言語	English
ホスト出版物のタイトル	2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers
ページ	C36-C37
出版ステータス	Published - 2013
イベント	2013 Symposium on VLSI Technology, VLSIT 2013 - Kyoto, Japan 継続期間: 2013 6月 11 → 2013 6月 13

出版物シリーズ

名前	Digest of Technical Papers - Symposium on VLSI Technology
ISSN（印刷版）	0743-1562

Other

Other	2013 Symposium on VLSI Technology, VLSIT 2013
国/地域	Japan
City	Kyoto
Period	13/6/11 → 13/6/13

UN SDG

この成果は、次の持続可能な開発目標に貢献しています

SDG 7 エネルギーをみんなに　そしてクリーンに

ASJC Scopus subject areas

電子工学および電気工学

他のファイルとリンク

フィンガープリント

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引用スタイル

Nomura, M., Muramatsu, A., Takeno, H., Hattori, S., Ogawa, D., Nasu, M., Hirairi, K., Kumashiro, S., Moriwaki, S., Yamamoto, Y., Miyano, S., Hiraku, Y., Hayashi, I., Yoshioka, K., Shikata, A., Ishikuro, H., Ahn, M., Okuma, Y., Zhang, X., ... Sakurai, T. (2013). 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. In 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers (pp. C36-C37). 記事 6576619 (Digest of Technical Papers - Symposium on VLSI Technology).

0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. / Nomura, M.; Muramatsu, A.; Takeno, H. その他.
2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers. 2013. p. C36-C37 6576619 (Digest of Technical Papers - Symposium on VLSI Technology).

研究成果: Conference contribution

Nomura, M, Muramatsu, A, Takeno, H, Hattori, S, Ogawa, D, Nasu, M, Hirairi, K, Kumashiro, S, Moriwaki, S, Yamamoto, Y, Miyano, S, Hiraku, Y, Hayashi, I, Yoshioka, K, Shikata, A, Ishikuro, H, Ahn, M, Okuma, Y, Zhang, X, Ryu, Y, Ishida, K, Takamiya, M, Kuroda, T, Shinohara, H & Sakurai, T 2013, 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. in 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers., 6576619, Digest of Technical Papers - Symposium on VLSI Technology, pp. C36-C37, 2013 Symposium on VLSI Technology, VLSIT 2013, Kyoto, Japan, 13/6/11.

Nomura M, Muramatsu A, Takeno H, Hattori S, Ogawa D, Nasu M その他. 0.5V image processor with 563 GOPS/W SIMD and 32bit CPU using high voltage clock distribution (HVCD) and adaptive frequency scaling (AFS) with 40nm CMOS. In 2013 Symposium on VLSI Technology, VLSIT 2013 - Digest of Technical Papers. 2013. p. C36-C37. 6576619. (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 \%, 13\%, and 6\%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33\%.",

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AU - Nomura, M.

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AU - Takeno, H.

AU - Hattori, S.

AU - Ogawa, D.

AU - Nasu, M.

AU - Hirairi, K.

AU - Kumashiro, S.

AU - Moriwaki, S.

AU - Yamamoto, Y.

AU - Miyano, S.

AU - Hiraku, Y.

AU - Hayashi, I.

AU - Yoshioka, K.

AU - Shikata, A.

AU - Ishikuro, H.

AU - Ahn, M.

AU - Okuma, Y.

AU - Zhang, X.

AU - Ryu, Y.

AU - Ishida, K.

AU - Takamiya, M.

AU - Kuroda, T.

AU - Shinohara, H.

AU - Sakurai, T.

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AB - A 0.5V, 10MHz, 9mW image processor with 320 processing element (PE) SIMD and a 32bit CPU has been developed using 40-nm CMOS. High voltage clock distribution (HVCD) reduces the number of excessive hold buffers required in a 0.5-V logic circuit design, thereby reducing the area, delay, and energy of the SIMD by 14 %, 13%, and 6%, respectively. The 0.5-V SIMD with HVCD achieves an energy efficiency of 563 GOPS/W (= 4.26mW at 7.5MHz), the highest yet reported for near-threshold SIMD. In addition, adaptive frequency scaling (AFS), used to mitigate the impact of the ripple of a buck converters, increases average clock frequency by 33%.

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