10-Gb/s (1.25 Gb/s×8) 4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration

Eiji Oki, Naoaki Yamanaka, Yusuke Ohtomo, Kazuhiko Okazaki, Ryusuke Kawano

研究成果: Article査読

21 被引用数 (Scopus)


This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4×2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSI's. To increase the LSI throughput and reduce the power consumption, we used 0.25-μm CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSI's, an 8×8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size.

ジャーナルIEEE Journal of Solid-State Circuits
出版ステータスPublished - 1999 12月

ASJC Scopus subject areas

  • 電子工学および電気工学


「10-Gb/s (1.25 Gb/s×8) 4×2 0.25-μm CMOS/SIMOX ATM switch based on scalable distributed arbitration」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。