2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito; Yasufumi Sugimori; Yoshinori Kohama; Yoichi Yoshida; Noriyuki Miura; Hiroki Ishikuro; Takayasu Sakurai; Tadahiro Kuroda

doi:10.1109/JSSC.2009.2034431

2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

研究成果: Article › 査読

10 被引用数 (Scopus)

抄録

An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.

本文言語	English
論文番号	5357556
ページ（範囲）	134-141
ページ数	8
ジャーナル	IEEE Journal of Solid-State Circuits
巻	45
号	1
DOI	https://doi.org/10.1109/JSSC.2009.2034431
出版ステータス	Published - 2010 1月 1

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/JSSC.2009.2034431

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title = "2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking",

abstract = "An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.",

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AU - Saito, Mitsuko

AU - Sugimori, Yasufumi

AU - Kohama, Yoshinori

AU - Yoshida, Yoichi

AU - Miura, Noriyuki

AU - Ishikuro, Hiroki

AU - Sakurai, Takayasu

AU - Kuroda, Tadahiro

PY - 2010/1/1

Y1 - 2010/1/1

N2 - An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.

AB - An inductive-coupling programmable bus for NAND flash memory access in Solid State Drive (SSD) is presented. Compared to the conventional SSD, this wireless interface using relayed transmission reduces power consumption to 1/2, I/O circuitlayout area to 1/40, and achieves a data rate of 2 Gb/s in 0.18 m CMOS process. In addition, since this wireless interface enables one package to contain 64 chips, the number of packages is reduced to 1/8.

KW - Chip to chip

KW - Inductive coupling

KW - Memory stacking

KW - SiP

KW - Three-dimensional

KW - Wireless interconnect

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2 Gb/s 15 pJ/b/chip inductive-coupling programmable bus for NAND flash memory stacking

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