TY - GEN
T1 - 34.5 A 818-4094TOPS/W Capacitor-Reconfigured CIM Macro for Unified Acceleration of CNNs and Transformers
AU - Yoshioka, Kentaro
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - In the rapidly evolving landscape of machine learning, workloads using diverse neural-network architectures must be covered: including CNNs for image processing, transformers for natural language processing (NLP), and hybrid architectures that blend CNNs and transformers for audio processing. As illustrated in Fig. 34.5.1, these varied architectures have unique computational precision requirements. While CNNs achieve satisfactory accuracy even with low-computational precision, compute SNR or CSNR[1], transformers require higher CSNR to reach their full potential. This diversity amplifies the need for versatile hardware accelerators that can efficiently handle both CNNs and transformers, while meeting the multifaceted demands of modern machine-learning applications.
AB - In the rapidly evolving landscape of machine learning, workloads using diverse neural-network architectures must be covered: including CNNs for image processing, transformers for natural language processing (NLP), and hybrid architectures that blend CNNs and transformers for audio processing. As illustrated in Fig. 34.5.1, these varied architectures have unique computational precision requirements. While CNNs achieve satisfactory accuracy even with low-computational precision, compute SNR or CSNR[1], transformers require higher CSNR to reach their full potential. This diversity amplifies the need for versatile hardware accelerators that can efficiently handle both CNNs and transformers, while meeting the multifaceted demands of modern machine-learning applications.
UR - https://www.scopus.com/pages/publications/85188073370
UR - https://www.scopus.com/pages/publications/85188073370#tab=citedBy
U2 - 10.1109/ISSCC49657.2024.10454489
DO - 10.1109/ISSCC49657.2024.10454489
M3 - Conference contribution
AN - SCOPUS:85188073370
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 574
EP - 576
BT - 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Solid-State Circuits Conference, ISSCC 2024
Y2 - 18 February 2024 through 22 February 2024
ER -