TY - JOUR
T1 - 50% active-power saving without speed degradation using standby power reduction (SPR) circuit
AU - Seta, Katsuhiro
AU - Hara, Hiroyuki
AU - Kuroda, Tadahiro
AU - Kakumu, Masakazu
AU - Sakurai, Takayasu
PY - 1995/2/1
Y1 - 1995/2/1
N2 - To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.
AB - To understand circuit delay and power dissipation dependence on power supply voltage (VDD) and threshold voltage (VTH) of MOSFETs, a typical logic circuit is investigated. Fanout is chosen to be 5 which corresponds to the statistical average of gate load in ASICs. If VTH is reduced to 0.3 V, VDD can be decreased down to 2 V while maintaining the speed at VTH = 0.7 V and VDD = 3 V which is the typical operation condition for high-speed LSIs. The active power dissipation, in this case, is reduced by more than 50%.
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M3 - Conference article
AN - SCOPUS:0029253931
SN - 0193-6530
VL - 38
SP - 318
EP - 319
JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
T2 - Proceedings of the 1995 IEEE International Solid-State Circuits Conference
Y2 - 15 February 1995 through 17 February 1995
ER -