5Gb/s 8 × 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200MHz LVDS interface

Yasuo Unekawa; Keiko Seki-Fukuda; Kenji Sakaue; Takehiko Nakao; Shin'ichi Yoshioka; Tetsu Nagamatsu; Hideaki Nakakita; Yasuyuki Kaneko; Masahiko Motoyama; Yoshihiro Ohba; Koutarou Ise; Masayoshi Ono; Kuniyuki Fujiwara; Yuichi Miyazawa; Tadahiro Kuroda; al et al

5Gb/s 8 × 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200MHz LVDS interface

Yasuo Unekawa, Keiko Seki-Fukuda, Kenji Sakaue, Takehiko Nakao, Shin'ichi Yoshioka, Tetsu Nagamatsu, Hideaki Nakakita, Yasuyuki Kaneko, Masahiko Motoyama, Yoshihiro Ohba, Koutarou Ise, Masayoshi Ono, Kuniyuki Fujiwara, Yuichi Miyazawa, Tadahiro Kuroda, al et al

研究成果: Conference article › 査読

21 被引用数 (Scopus)

抄録

The switch element (SE) is a 622Mb/s, 8×8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5Gbps bandwidth, supporting 5 QoS classes delay priority and link-by-link multicast. Up to a 32×32 switch with 20Gbps bandwidth can be configured using multiple SEs and distributor/arbiter LSIs.

本文言語	English
ページ（範囲）	118-119
ページ数	2
ジャーナル	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
巻	39
出版ステータス	Published - 1996 2月 1
外部発表	はい
イベント	Proceedings of the 1996 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA 継続期間: 1996 2月 8 → 1996 2月 10

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

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引用スタイル

Unekawa, Y., Seki-Fukuda, K., Sakaue, K., Nakao, T., Yoshioka, S., Nagamatsu, T., Nakakita, H., Kaneko, Y., Motoyama, M., Ohba, Y., Ise, K., Ono, M., Fujiwara, K., Miyazawa, Y., Kuroda, T., & et al, A. (1996). 5Gb/s 8 × 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200MHz LVDS interface. Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 39, 118-119.

Unekawa, Y, Seki-Fukuda, K, Sakaue, K, Nakao, T, Yoshioka, S, Nagamatsu, T, Nakakita, H, Kaneko, Y, Motoyama, M, Ohba, Y, Ise, K, Ono, M, Fujiwara, K, Miyazawa, Y, Kuroda, T & et al, A 1996, '5Gb/s 8 × 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200MHz LVDS interface', Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 39, pp. 118-119.

@article{ca9c1814d788427594a15e2ccb9f09df,

title = "5Gb/s 8 × 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200MHz LVDS interface",

abstract = "The switch element (SE) is a 622Mb/s, 8×8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5Gbps bandwidth, supporting 5 QoS classes delay priority and link-by-link multicast. Up to a 32×32 switch with 20Gbps bandwidth can be configured using multiple SEs and distributor/arbiter LSIs.",

author = "Yasuo Unekawa and Keiko Seki-Fukuda and Kenji Sakaue and Takehiko Nakao and Shin'ichi Yoshioka and Tetsu Nagamatsu and Hideaki Nakakita and Yasuyuki Kaneko and Masahiko Motoyama and Yoshihiro Ohba and Koutarou Ise and Masayoshi Ono and Kuniyuki Fujiwara and Yuichi Miyazawa and Tadahiro Kuroda and {et al}, al",

year = "1996",

month = feb,

day = "1",

language = "English",

volume = "39",

pages = "118--119",

journal = "Digest of Technical Papers - IEEE International Solid-State Circuits Conference",

issn = "0193-6530",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1996 IEEE International Solid-State Circuits Conference ; Conference date: 08-02-1996 Through 10-02-1996",

}

TY - JOUR

T1 - 5Gb/s 8 × 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200MHz LVDS interface

AU - Unekawa, Yasuo

AU - Seki-Fukuda, Keiko

AU - Sakaue, Kenji

AU - Nakao, Takehiko

AU - Yoshioka, Shin'ichi

AU - Nagamatsu, Tetsu

AU - Nakakita, Hideaki

AU - Kaneko, Yasuyuki

AU - Motoyama, Masahiko

AU - Ohba, Yoshihiro

AU - Ise, Koutarou

AU - Ono, Masayoshi

AU - Fujiwara, Kuniyuki

AU - Miyazawa, Yuichi

AU - Kuroda, Tadahiro

AU - et al, al

PY - 1996/2/1

Y1 - 1996/2/1

N2 - The switch element (SE) is a 622Mb/s, 8×8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5Gbps bandwidth, supporting 5 QoS classes delay priority and link-by-link multicast. Up to a 32×32 switch with 20Gbps bandwidth can be configured using multiple SEs and distributor/arbiter LSIs.

AB - The switch element (SE) is a 622Mb/s, 8×8 shared-buffer ATM switch LSI for backbone LAN and WAN applications. The SE has 5Gbps bandwidth, supporting 5 QoS classes delay priority and link-by-link multicast. Up to a 32×32 switch with 20Gbps bandwidth can be configured using multiple SEs and distributor/arbiter LSIs.

UR - http://www.scopus.com/inward/record.url?scp=0030085999&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030085999&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0030085999

SN - 0193-6530

VL - 39

SP - 118

EP - 119

JO - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

JF - Digest of Technical Papers - IEEE International Solid-State Circuits Conference

T2 - Proceedings of the 1996 IEEE International Solid-State Circuits Conference

Y2 - 8 February 1996 through 10 February 1996

ER -

5Gb/s 8 × 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200MHz LVDS interface

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ASJC Scopus subject areas

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