7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Kentaro Yoshioka; Ryo Saito; Takumi Danjo; Sanroku Tsukamoto; Hiroki Ishikuro

doi:10.1109/VLSIC.2014.6858374

7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro

電気情報工学科

研究成果: Conference contribution

8 被引用数 (Scopus)

抄録

Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

本文言語	English
ホスト出版物のタイトル	2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（印刷版）	9781479933273
DOI	https://doi.org/10.1109/VLSIC.2014.6858374
出版ステータス	Published - 2014 1月 1
イベント	28th IEEE Symposium on VLSI Circuits, VLSIC 2014 - Honolulu, HI, United States 継続期間: 2014 6月 10 → 2014 6月 13

出版物シリーズ

名前	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	28th IEEE Symposium on VLSI Circuits, VLSIC 2014
国/地域	United States
City	Honolulu, HI
Period	14/6/10 → 14/6/13

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

文献へのアクセス

10.1109/VLSIC.2014.6858374

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引用スタイル

Yoshioka, K., Saito, R., Danjo, T., Tsukamoto, S., & Ishikuro, H. (2014). 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers 記事 6858374 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2014.6858374

7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. / Yoshioka, Kentaro; Saito, Ryo; Danjo, Takumi その他.
2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. 6858374 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

研究成果: Conference contribution

Yoshioka, K, Saito, R, Danjo, T, Tsukamoto, S & Ishikuro, H 2014, 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. in 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers., 6858374, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, Institute of Electrical and Electronics Engineers Inc., 28th IEEE Symposium on VLSI Circuits, VLSIC 2014, Honolulu, HI, United States, 14/6/10. https://doi.org/10.1109/VLSIC.2014.6858374

Yoshioka K, Saito R, Danjo T, Tsukamoto S, Ishikuro H. 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. In 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2014. 6858374. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2014.6858374

Yoshioka, Kentaro ; Saito, Ryo ; Danjo, Takumi その他. / 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2014. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{f360d2cf3b0248b9a91d8b8f0db75141,

title = "7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique",

abstract = "Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.",

author = "Kentaro Yoshioka and Ryo Saito and Takumi Danjo and Sanroku Tsukamoto and Hiroki Ishikuro",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/VLSIC.2014.6858374",

language = "English",

isbn = "9781479933273",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers",

note = "28th IEEE Symposium on VLSI Circuits, VLSIC 2014 ; Conference date: 10-06-2014 Through 13-06-2014",

}

TY - GEN

T1 - 7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

AU - Yoshioka, Kentaro

AU - Saito, Ryo

AU - Danjo, Takumi

AU - Tsukamoto, Sanroku

AU - Ishikuro, Hiroki

PY - 2014/1/1

Y1 - 2014/1/1

N2 - Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

AB - Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

UR - http://www.scopus.com/inward/record.url?scp=84905659274&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84905659274&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2014.6858374

DO - 10.1109/VLSIC.2014.6858374

M3 - Conference contribution

AN - SCOPUS:84905659274

SN - 9781479933273

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

BT - 2014 Symposium on VLSI Circuits, VLSIC 2014 - Digest of Technical Papers

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 28th IEEE Symposium on VLSI Circuits, VLSIC 2014

Y2 - 10 June 2014 through 13 June 2014

ER -