A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Yasuyuki Hiraku; Isamu Hayashi; Hayun Chung; Tadahiro Kuroda; Hiroki Ishikuro

doi:10.1109/IPEC.2012.6522616

A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

Yasuyuki Hiraku, Isamu Hayashi, Hayun Chung, Tadahiro Kuroda, Hiroki Ishikuro

電気情報工学科

研究成果: Paper › 査読

11 被引用数 (Scopus)

抄録

This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm².

本文言語	English
ページ	33-36
ページ数	4
DOI	https://doi.org/10.1109/IPEC.2012.6522616
出版ステータス	Published - 2012
イベント	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012 - Kobe, Japan 継続期間: 2012 11月 12 → 2012 11月 14

Other

Other	2012 IEEE Asian Solid-State Circuits Conference, A-SSCC 2012
国/地域	Japan
City	Kobe
Period	12/11/12 → 12/11/14

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/IPEC.2012.6522616

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引用スタイル

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title = "A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS",

abstract = "This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2.",

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doi = "10.1109/IPEC.2012.6522616",

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AU - Hayashi, Isamu

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AU - Kuroda, Tadahiro

AU - Ishikuro, Hiroki

PY - 2012

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AB - This paper presents an ultra-low-voltage and low-power all-digital (AD) PLL. The AD-PLL consists of time-to-digital converter (TDC) combined 8-phase digitally controlled ring oscillator. The proposed AD-PLL eliminates a delay-line based TDC and suited for ultra-low-voltage and low-power operation in wide frequency range. The AD-PLL designed and fabricated in 40nm-CMOS technology operates with power consumption of 45.5μ\ν at 0.5V power supply and 100MHz output frequency. The AD-PLL has power scalability from 10MHz to 100MHz with normalized power consumption lower than 0.47μW/μηz. The core area is 0.037mm2.

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A 0.5V 10MHz-to-100MHz 0.47μz power scalable AD-PLL in 40nm CMOS

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