A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

Akira Shikata; Ryota Sekimoto; Tadahiro Kuroda; Hiroki Ishikuro

A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

研究成果: Conference contribution

抄録

This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

本文言語	English
ホスト出版物のタイトル	2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
ページ	262-263
ページ数	2
出版ステータス	Published - 2011 9月 16
イベント	2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan 継続期間: 2011 6月 15 → 2011 6月 17

出版物シリーズ

名前	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other	2011 Symposium on VLSI Circuits, VLSIC 2011
国/地域	Japan
City	Kyoto
Period	11/6/15 → 11/6/17

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

他のファイルとリンク

引用スタイル

Shikata, A, Sekimoto, R, Kuroda, T & Ishikuro, H 2011, A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS. in 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers., 5986444, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 262-263, 2011 Symposium on VLSI Circuits, VLSIC 2011, Kyoto, Japan, 11/6/15.

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abstract = "This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.",

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N2 - This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

AB - This paper presents an extremely low-voltage operation and power efficient successive-approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is proposed to relax the speed requirement of the comparator and decrease the resolution of internal Digital-to-Analog Converter (DAC) by 1-bit. The internal DAC employs unit capacitance of 0.5fF and ADC operates at nearly thermal noise limitation. To deal with the problem of capacitor mismatch, reconfigurable capacitor array and calibration procedure were developed. The prototype ADC fabricated using 40nm CMOS process achieves 46.8dB SNDR with 1.1MS/sec at 0.5V power supply. The FoM is 6.3-fJ/conversion step.

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BT - 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers

T2 - 2011 Symposium on VLSI Circuits, VLSIC 2011

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A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with tri-level comparator in 40nm CMOS

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ASJC Scopus subject areas

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