A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Tadahiro Kuroda; Tetsuya Fujita; Shinji Mita; Tetsu Nagamatsu; Shinichi Yoshioka; Kojiro Suzuki; Fumihiko Sano; Masayuki Norishima; Masayuki Murota; Makoto Kako; Masaaki Kinugawa; Masakazu Kakumu; Takayasu Sakurai

doi:10.1109/jssc.1996.542322

A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakumu, Takayasu Sakurai

研究成果: Article › 査読

323 被引用数 (Scopus)

抄録

A 4 mm², two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore V_DD -V_th, design space is also studied.

本文言語	English
ページ（範囲）	1770-1777
ページ数	8
ジャーナル	IEEE Journal of Solid-State Circuits
巻	31
号	11
DOI	https://doi.org/10.1109/jssc.1996.542322
出版ステータス	Published - 1996 11月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/jssc.1996.542322

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引用スタイル

Kuroda, T., Fujita, T., Mita, S., Nagamatsu, T., Yoshioka, S., Suzuki, K., Sano, F., Norishima, M., Murota, M., Kako, M., Kinugawa, M., Kakumu, M., & Sakurai, T. (1996). A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme. IEEE Journal of Solid-State Circuits, 31(11), 1770-1777. https://doi.org/10.1109/jssc.1996.542322

Kuroda, T, Fujita, T, Mita, S, Nagamatsu, T, Yoshioka, S, Suzuki, K, Sano, F, Norishima, M, Murota, M, Kako, M, Kinugawa, M, Kakumu, M & Sakurai, T 1996, 'A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme', IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1770-1777. https://doi.org/10.1109/jssc.1996.542322

@article{0407df7615d54ea581cbe8c737398b8d,

title = "A 0.9-V, 150-MHz, 10-mW, 4 mm{"}, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme",

abstract = "A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD -Vth, design space is also studied.",

author = "Tadahiro Kuroda and Tetsuya Fujita and Shinji Mita and Tetsu Nagamatsu and Shinichi Yoshioka and Kojiro Suzuki and Fumihiko Sano and Masayuki Norishima and Masayuki Murota and Makoto Kako and Masaaki Kinugawa and Masakazu Kakumu and Takayasu Sakurai",

year = "1996",

month = nov,

doi = "10.1109/jssc.1996.542322",

language = "English",

volume = "31",

pages = "1770--1777",

journal = "IEEE Journal of Solid-State Circuits",

issn = "0018-9200",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

AU - Kuroda, Tadahiro

AU - Fujita, Tetsuya

AU - Mita, Shinji

AU - Nagamatsu, Tetsu

AU - Yoshioka, Shinichi

AU - Suzuki, Kojiro

AU - Sano, Fumihiko

AU - Norishima, Masayuki

AU - Murota, Masayuki

AU - Kako, Makoto

AU - Kinugawa, Masaaki

AU - Kakumu, Masakazu

AU - Sakurai, Takayasu

PY - 1996/11

Y1 - 1996/11

N2 - A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD -Vth, design space is also studied.

AB - A 4 mm2, two-dimensional (2-D) 8 × 8 discrete cosine transform (DCT) core processor for HDTV-resolution video compression/decompression in a 0.3-μm CMOS triple-well, double-metal technology operates at 150 MHz from a 0.9-V power supply and consumes 10 mW, only 2% power dissipation of a previous 3.3-V design. Circuit techniques for dynamically varying threshold voltage (VT scheme) are introduced to reduce active power dissipation with negligible overhead in speed, standby power dissipation, and chip area. A way to explore VDD -Vth, design space is also studied.

UR - http://www.scopus.com/inward/record.url?scp=0030285492&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0030285492&partnerID=8YFLogxK

U2 - 10.1109/jssc.1996.542322

DO - 10.1109/jssc.1996.542322

M3 - Article

AN - SCOPUS:0030285492

SN - 0018-9200

VL - 31

SP - 1770

EP - 1777

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

IS - 11

ER -

A 0.9-V, 150-MHz, 10-mW, 4 mm", 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme

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