A 1 TB/s 1 pJ/b 6.4 mm 2/TB/s QDR inductive-coupling interface between 65-nm CMOS logic and emulated 100-nm DRAM

Noriyuki Miura; Mitsuko Saito; Tadahiro Kuroda

doi:10.1109/JETCAS.2012.2193836

A 1 TB/s 1 pJ/b 6.4 mm ²/TB/s QDR inductive-coupling interface between 65-nm CMOS logic and emulated 100-nm DRAM

Noriyuki Miura, Mitsuko Saito, Tadahiro Kuroda

研究成果: Article › 査読

22 被引用数 (Scopus)

抄録

1 TB/s 1 pJ/b 6.4 mm ²/TB/s inductive-coupling interface between 65-nm complementary metal-oxide-semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <10 ^-16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 ×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.

本文言語	English
論文番号	6199998
ページ（範囲）	249-256
ページ数	8
ジャーナル	IEEE Journal on Emerging and Selected Topics in Circuits and Systems
巻	2
号	2
DOI	https://doi.org/10.1109/JETCAS.2012.2193836
出版ステータス	Published - 2012

ASJC Scopus subject areas

電子工学および電気工学

UN SDG

この成果は、次の持続可能な開発目標に貢献しています

文献へのアクセス

10.1109/JETCAS.2012.2193836

他のファイルとリンク

引用スタイル

@article{d80d7f2d0dc94a1db7e120c129d8ccbe,

title = "A 1 TB/s 1 pJ/b 6.4 mm 2/TB/s QDR inductive-coupling interface between 65-nm CMOS logic and emulated 100-nm DRAM",

abstract = "1 TB/s 1 pJ/b 6.4 mm 2/TB/s inductive-coupling interface between 65-nm complementary metal-oxide-semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <10 -16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 ×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.",

keywords = "High-bandwidth interface, inductive coupling, memory-processor stacking, three-dimensional integration",

author = "Noriyuki Miura and Mitsuko Saito and Tadahiro Kuroda",

note = "Funding Information: Manuscript received December 30, 2011; revised March 09, 2012; accepted March 24, 2012. Date of publication May 14, 2012; date of current version June 07, 2012. This work was supported by CREST/JST. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with STARC, e-Shuttle, Inc., and Fujitsu Ltd. This paper was recommended by Guest Editor K. Choi.",

year = "2012",

doi = "10.1109/JETCAS.2012.2193836",

language = "English",

volume = "2",

pages = "249--256",

journal = "IEEE Journal on Emerging and Selected Topics in Circuits and Systems",

issn = "2156-3357",

publisher = "IEEE Circuits and Systems Society",

number = "2",

}

TY - JOUR

T1 - A 1 TB/s 1 pJ/b 6.4 mm 2/TB/s QDR inductive-coupling interface between 65-nm CMOS logic and emulated 100-nm DRAM

AU - Miura, Noriyuki

AU - Saito, Mitsuko

AU - Kuroda, Tadahiro

N1 - Funding Information: Manuscript received December 30, 2011; revised March 09, 2012; accepted March 24, 2012. Date of publication May 14, 2012; date of current version June 07, 2012. This work was supported by CREST/JST. The VLSI chip in this study has been fabricated in the chip fabrication program of VDEC, the University of Tokyo in collaboration with STARC, e-Shuttle, Inc., and Fujitsu Ltd. This paper was recommended by Guest Editor K. Choi.

PY - 2012

Y1 - 2012

N2 - 1 TB/s 1 pJ/b 6.4 mm 2/TB/s inductive-coupling interface between 65-nm complementary metal-oxide-semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <10 -16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 ×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.

AB - 1 TB/s 1 pJ/b 6.4 mm 2/TB/s inductive-coupling interface between 65-nm complementary metal-oxide-semiconductor (CMOS) logic and emulated 100-nm dynamic random access memory (DRAM) is developed. BER <10 -16 operation is examined in 1024-bit parallel links. Compared to the latest wired 40-nm DRAM interface, the bandwidth is increased to 32 ×, and the energy consumption and the layout area are reduced to 1/8 and 1/22, respectively.

KW - High-bandwidth interface

KW - inductive coupling

KW - memory-processor stacking

KW - three-dimensional integration

UR - http://www.scopus.com/inward/record.url?scp=84862336016&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84862336016&partnerID=8YFLogxK

U2 - 10.1109/JETCAS.2012.2193836

DO - 10.1109/JETCAS.2012.2193836

M3 - Article

AN - SCOPUS:84862336016

SN - 2156-3357

VL - 2

SP - 249

EP - 256

JO - IEEE Journal on Emerging and Selected Topics in Circuits and Systems

JF - IEEE Journal on Emerging and Selected Topics in Circuits and Systems

IS - 2

M1 - 6199998

ER -