TY - GEN
T1 - A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL
AU - Urano, Yuki
AU - Yun, Won Joo
AU - Kuroda, Tadahiro
AU - Ishikuro, Hiroki
PY - 2013/9/9
Y1 - 2013/9/9
N2 - This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.
AB - This paper presents an all-digital CDR with TDC combined DLL which can be used for not only NRZ signaling but also pulse-based communication. The TDC combined DLL can realize a small area, low power and fast locking by sharing the delay line of the TDC with the DLL. The proposed CDR can recover the clock by evaluating a waveform of one cycle, and detect edge from a pulse-based signal. Locking time is within 8 clock cycles, and power efficiency is 1.26mW/GHz at 1Gbps and 0.7V power supply. The rms and peak-to-peak jitter at 2.3Gbps and 1.0V are 5.44ps and 37.4ps, respectively. Die area is 0.0297mm2.
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U2 - 10.1109/ISCAS.2013.6572161
DO - 10.1109/ISCAS.2013.6572161
M3 - Conference contribution
AN - SCOPUS:84883317499
SN - 9781467357609
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1576
EP - 1579
BT - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
T2 - 2013 IEEE International Symposium on Circuits and Systems, ISCAS 2013
Y2 - 19 May 2013 through 23 May 2013
ER -