抄録
A wireless interface by inductive coupling achieves aggregated data rate of 195 Gb/s with power dissipation of 1.2W among 4-stacked chips in a package where 195 transceivers with the data rate of 1 Gb/s/channel are arranged in 50-/spl mu/m pitch in 0.25-/spl mu/m CMOS technology. By thinning chip thickness to 10/spl mu/m, the interface communicates at distance of 15 /spl mu/ m at minimum and 43 /spl mu/m at maximum. A low-power single-end transmitter achieves 55% power reduction for multiple connections. The transmit power is dynamically controlled in accordance with communication distance to reduce not only power dissipation but also crosstalk.
| 本文言語 | English |
|---|---|
| ページ(範囲) | 23-34 |
| ページ数 | 12 |
| ジャーナル | IEEE Journal of Solid-State Circuits |
| 巻 | 41 |
| 号 | 1 |
| DOI | |
| 出版ステータス | Published - 2006 1月 |
ASJC Scopus subject areas
- 電子工学および電気工学
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