A 1Tb/s 3W inductive-coupling transceiver chip

Noriyuki Miura; Tadahiro Kuroda

doi:10.1109/ASPDAC.2007.357798

A 1Tb/s 3W inductive-coupling transceiver chip

Noriyuki Miura, Tadahiro Kuroda

研究成果: Conference contribution

12 被引用数 (Scopus)

抄録

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm ². The total layout area including 16 clock transceivers is 2mm ² in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 ^-13 with 150ps timing margin.

本文言語	English
ホスト出版物のタイトル	Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
ページ	92-93
ページ数	2
DOI	https://doi.org/10.1109/ASPDAC.2007.357798
出版ステータス	Published - 2007 12月 1
イベント	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007 - Yokohama, Japan 継続期間: 2007 1月 23 → 2007 1月 27

出版物シリーズ

名前	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007
国/地域	Japan
City	Yokohama
Period	07/1/23 → 07/1/27

ASJC Scopus subject areas

コンピュータサイエンスの応用
コンピュータグラフィックスおよびコンピュータ支援設計
電子工学および電気工学

文献へのアクセス

10.1109/ASPDAC.2007.357798

他のファイルとリンク

引用スタイル

Miura, N & Kuroda, T 2007, A 1Tb/s 3W inductive-coupling transceiver chip. in Proceedings of the ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007., 4196002, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 92-93, ASP-DAC 2007 - Asia and South Pacific Design Automation Conference 2007, Yokohama, Japan, 07/1/23. https://doi.org/10.1109/ASPDAC.2007.357798

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abstract = "A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30μm in a layout area of 1mm 2. The total layout area including 16 clock transceivers is 2mm 2 in 0.18μm CMOS and the chip thickness is reduced to 10μm. Simple yet accurate model of inductive coupling is utilized for transceiver design. Bi-Phase Modulation (BPM) is employed for the data link to improve noise immunity, reducing power in the transceiver. 4-phase Time Division Multiplexing (TDM) reduces crosstalk and channel pitch. The BER is lower than 10 -13 with 150ps timing margin.",

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A 1Tb/s 3W inductive-coupling transceiver chip

抄録

出版物シリーズ

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ASJC Scopus subject areas

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