A 2 Gb/s Expandable Space-Division Switching LSI and Network Architecture for Gigabit-Rate Broad-Band Circuit Switching

Naoaki Yamanaka; Shiro Kikuchi; Masao Suzuki; Yukiharu Yoshioka

doi:10.1109/49.62833

A 2 Gb/s Expandable Space-Division Switching LSI and Network Architecture for Gigabit-Rate Broad-Band Circuit Switching

Naoaki Yamanaka, Shiro Kikuchi, Masao Suzuki, Yukiharu Yoshioka

研究成果: Article › 査読

2 被引用数 (Scopus)

抄録

A new expandable space-division (SD) switch architecture and a bipolar circuit design for Gb/s crosspoint switch LSI's are described. An expandable 2 Gb/s 16 x 16 crosspoint switch LSI is developed which employs a new switch structure, a new circuit design, and a super self-aligned process (SST-1A). A new switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and new switching network architecture, an experimental 620 Mb/s network system is demonstrated.

本文言語	English
ページ（範囲）	1543-1550
ページ数	8
ジャーナル	IEEE Journal on Selected Areas in Communications
巻	8
号	8
DOI	https://doi.org/10.1109/49.62833
出版ステータス	Published - 1990 10月
外部発表	はい

ASJC Scopus subject areas

コンピュータネットワークおよび通信
電子工学および電気工学

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10.1109/49.62833

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A 2 Gb/s Expandable Space-Division Switching LSI and Network Architecture for Gigabit-Rate Broad-Band Circuit Switching

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