A 2.2 gbit/s si bipolar 8 × 8 crosspoint switching LSI

Naoaki Yamanaka, Shiro Kikuchi, Masao Suzuki, Michihiro Hirata

研究成果: Article査読

1 被引用数 (Scopus)

抄録

A high‐speed 8 × 8 space‐division switching LSI has been developed for video and HDTV switching and broadcasting applications in the future B‐ISDN. The LSI employs a new circuit design and super self‐aligned process technology (SST−1A), and is switched successfully with a bit error rate of less than 10−9 at 2.5 Gbit/s using a 29−1 pseudorandom NRZ sequence. Pulse jitter has been limited to less than 70 ps at 2.2 Gbit/s by utilizing a small internal voltage swing (225 mV) employing a differential CML cell. The LSI has an ECL‐compatible interface, −4.0 V and −2.0 V power supply voltages, and power dissipation of less than 997 mW. High‐speed address control memories (ACMs) are integrated mono‐lithically into the LSI, which can operate both synchronously and asynchronously. Using several of these LSIs, a three‐stage switching network prototype system has been demonstrated. This network brings us closer to realizing a large‐scale, gigabit‐order, high‐speed switching network for B‐ISDN.

本文言語English
ページ(範囲)100-110
ページ数11
ジャーナルElectronics and Communications in Japan (Part II: Electronics)
74
2
DOI
出版ステータスPublished - 1991
外部発表はい

ASJC Scopus subject areas

  • 物理学および天文学一般
  • コンピュータ ネットワークおよび通信
  • 電子工学および電気工学

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